[paper] Compact device modeling and simulation with Qucs/Qucs-S/Xyce modular libraries

Mike Brinson and Felix Salfelder 

Compact device modeling and simulation with Qucs/Qucs-S/Xyce modular libraries 

In 28th MIXDES (2021), pp. 35-40 

DOI: 10.23919/MIXDES52406.2021.9497545 

Abstract—The rapid development of new semiconductor materials and devices has highlighted the need for compact modeling and circuit simulation tools that can be easily adapted to accommodate emerging technologies. In most instances device modeling tools employ non-linear behavioural sources and Verilog-A modules for model prototype construction. This paper is concerned with the properties and application of modular user defined/plugin library toolkit that combines the best features of behavioural source and Verilog-A modeling practice while encouraging user extensions. The toolkit has been implemented as a Qucs/Qucs-S/Xyce modular library that is loadable on demand. To demonstrate its capabilities and flexibility a series of compact device models are introduced and their simulated performance presented and evaluated.

Fig: A Qucs-S/Xyce test bench for simulating and displaying BJT Ic/V ce

output characteristics with 1µA ≤ Ib ≤ 10µA in 1µA steps.

[paper] eSim: An Open Source EDA Tool

Rahul Paknikar, Saurabh Bansode, Gloria Nandihal, Madhav P. Desai, Kannan M. Moudgalya, 

and Ashutosh Jha*

eSim: An Open Source EDA Tool for Mixed-Signal and Microcontroller Simulations

4th International Conference on Circuits, Systems and Simulation

(ICCSS), 2021, pp. 212-217,

DOI: 10.1109/ICCSS51193.2021.9464198.

Indian Institute of Technology Bombay, Mumbai, Maharashtra, India
* Vellore Institute of Technology Chennai, Tamil Nadu, India

Abstract: The ability to carry out simulations before making a PCB can save a lot of time, effort and cost. This work explains the creation of an open source mixed-signal simulation software eSim that will be of great help to students, hobbyists, the SME sector and startups. Analog and digital components are respectively modelled using SPICE and a hardware descriptive language in eSim. Inclusion of AVR based microcontroller as a part of the digital circuit is demonstrated through its instructions implemented as a C code library. This methodology could be used to provide support to other microcontroller families, such as PIC, STM and also more sophisticated controllers. These concepts are demonstrated through a few examples.

Fig: Workflow of NGHDL

Acknowledgment: The authors would like to thank Prof. Pramod Murali, Department of Electrical Engineering, IIT Bombay and Mrs. Usha Viswanathan, FOSSEE, IIT Bombay for their guidance. We would also like to express our gratitude towards Powai Labs Technology Private Limited for their gratis contribution to the VHPIDIRECT package and Utility package of NGHDL. The FOSSEE project is funded by the National Mission on Education through ICT, Ministry of Education, Govt. of India.

Qucs-S as R&D design software

Qucs-S 

is not a simple circuit simulator, but also a research software. Please cite your R&D articles, if you are using Qucs-S in your research.

Documentation

• Main documentation page at readthedocs.io
• Presentation at the Spring MOS-AK 2016 at Lausanne
• Presentation at the Spring MOS-AK 2017 at Lausanne
• Presentation at the MIXDES2017 conference: Part 1 and Part 2

Publications

Qucs-S is not a simple circuit simulator, but also a research software. Please cite our articles, if you are using Qucs-S in your research.

1. Brinson, M. E., and Kuznetsov, V. (2016) A new approach to compact semiconductor device modelling with Qucs Verilog-A analogue module synthesis. Int. J. Numer. Model., 29: 1070-1088. (BibTeX)
2. D. Tomaszewski, G. Głuszko, M. Brinson, V. Kuznetsov and W. Grabinski, "FOSS as an efficient tool for extraction of MOSFET compact model parameters," 2016 MIXDES - 23rd International Conference Mixed Design of Integrated Circuits and Systems, Lodz, 2016, pp. 68-73. (BibTeX)
3. M. Brinson and V. Kuznetsov, "Qucs-0.0.19S: A new open-source circuit simulator and its application for hardware design," 2016 International Siberian Conference on Control and Communications (SIBCON), Moscow, 2016, pp. 1-5. (BibTeX)
4. M. Brinson and V. Kuznetsov, "Improvements in Qucs-S equation-defined modelling of semiconductor devices and IC's," 2017 MIXDES - 24th International Conference "Mixed Design of Integrated Circuits and Systems, Bydgoszcz, 2017, pp. 137-142. (BibTeX)
5. M. Brinson and V. Kuznetsov, "Extended behavioural device modelling and circuit simulation with Qucs-S" International Journal of Electronics, 2017, pp.1 - 14 (BibTeX)

[paper] Recent Developments in Qucs-S Equation-Defined Modelling of Semiconductor Devices and IC’s

Recent Developments in Qucs-S Equation-Defined Modelling of Semiconductor Devices and IC’s

Mike Brinson, and Vadim Kuznetsov

International Journal of Microelectronics and Computer Science

2017, Volume 8, Number 1 

ISSN 2080-8755 / eISSN 2353-9607

Abstract—The Qucs Equation-Defined Device was introduce roughly ten years ago as a versatile behavioural simulation component for modelling the non-linear static and dynamic properties of passive components, semiconductor devices and IC macromodels. Today, this component has become an established element for building experimental device simulation models. It’s inherent interactive properties make it ideal for device and circuit modelling via Qucs schematics. Moreover, Equation-Defined Devices often promote a clearer understanding of the factors involved in the construction of complex compact semiconductor simulation models. This paper is concerned with recent advances in Qucs-S/Ngspice/XSPICE modelling capabilities that improve model construction and simulation run time performance of Equation-Defined Devices using XSPICE model syntheses. To illustrate the new Qucs-S modelling techniques an XSPICE version of the EPFL EKV v2.6 long channel transistor model together with other illustrative examples are described and their performance simulated with Qucs-S and Ngspice [read more...]

Fig: EKV2.6 Qucs-S long channel static I/V model test bench and typical simulated I/V output characteristics as Qucs-S Equation-Defined Model

Qucs Roadmap

The QUCS Roadmap should serve as base to track the status of each action point. Enhancements can be handled in two ways:

• For simpler enhancements an issue/bug ticket shall be created and referenced back here. The pertinent discussion and documentation should be done on the body of each ticket.
• For more complex enhancements a Qucs Enhancement Proposal should be created and reference back here.

The open action points can be further categorized concerning the difficulty or amount of work as (Easy, Medium, Hard) and priority (0-3, 0 is the highest). See the Port to Qt4 / Qt5 for an example. Tickets will be tracked individually and assigned to milestones leading to stable releases.

Stage 1 - Simple GUI and simulator  

Stage 2 - Implementation of powerful circuit analysis tools

Stage 3 - Support for more design and synthesis tools  

Stage 4 - Implementation of industry standard device models

Stage 5 - Design realization, production, verification

Read more about QUCS Roadmap

[paper] RF-MEMS for Future Mobile Applications: Experimental Verification of a Reconfigurable 8-Bit Power Attenuator up to 110 GHz

RF-MEMS for Future Mobile Applications: Experimental Verification of a Reconfigurable 8-Bit Power Attenuator up to 110 GHz
Jacopo Iannacci¹ and Christian Tschoban^2
1Center for Materials and Microsystems - CMM, Fondazione Bruno Kessler , Trento, ITALY
²Fraunhofer Institut für Zuverlässigkeit und Mikrointegration IZM , Berlin, GERMANY
Journal of Micromechanics and Microengineering
Accepted Manuscript online 8 February 2017

Abstract

RF-MEMS technology is indicated as a key enabling solution to realise the high-performance and highly-reconfigurable passive components that future 5G communication standards will demand for. In this work, we present, test and discuss a novel design concept of an 8-bit reconfigurable power attenuator manufactured in the RF-MEMS technology available at the CMM-FBK, in Italy. The device features electrostatically controlled MEMS ohmic switches, in order to select/deselect resistive loads (both in series and shunt configuration) that attenuate the RF signal, and comprises 8 cascaded stages (i.e. 8-bit), thus implementing 256 different network configurations. Fabricated samples are measured (S-parameters) from 10 MHz to 110 GHz in a wide range of different configurations, and modelled/simulated in Ansys HFSS. The device exhibits attenuation levels (S21) in the range from -10 dB to -60 dB, up to 110 GHz. In particular, the S21 shows flatness from 15 dB down to 3-5 dB, from 10 MHz to 50 GHz, while less linear traces up to 110 GHz. Comprehensive discussion is developed around the Voltage Standing Wave Ratio (VSWR), employed as quality indicator for the attenuation levels. Margins of improvement at design level are also discussed, in order to overcome the limitations of the presented RF-MEMS device. The results of S-parameter simulations performed in the Quite Universal Circuit Simulator (QUCS: qucs.sourceforge.net) for a few significant configurations of the RF-MEMS attenuator from 10MHz to 110GHz are reported, too. [read more...]

QUCS mentioned in IEEE-EDL paper

Jacopo Iannacci, Fondazione Bruno Kessler (FBK), Trento, Italy, has recently published an article in the IEEE Electron Device Letters (EDL) where he used and explicitly mentioned the QUCS, FOSS CAD/EDA simulator:

RF-MEMS Technology for Future Mobile and High-Frequency Applications:

Reconfigurable 8-Bit Power Attenuator Tested up to 110 GHz

J. Iannacci, M. Huhn, C. Tschoban and H. Pötter

in IEEE EDL, vol. 37, no. 12, pp. 1646-1649, Dec. 2016.

Abstract: In this letter, we present and test—to the best of our knowledge, for the first time—, an 8-bit (256-state) reconfigurable RF-MEMS attenuator, from 10 MHz up to 110 GHz, realized in the CMM-FBK technology. Resistive loads, in series and shunt configuration, are selectively inserted on the RF line by means of electrostatic MEMS ohmic switches. The network exhibits several attenuation levels in the range of −10/−45 dB that are rather flat up to 50 GHz, and a certain number of configurations with VSWR smaller than 4 from nearly dc up to 110 GHz, and better than 2 on a frequency span of ~80 GHz.

doi: 10.1109/LED.2016.2623328

[read more: http://ieeexplore.ieee.org/stamp/stamp.jsp?tp=&arnumber=7726036&isnumber=7739309]

FOSDEM 2017 EDA Devroom Call for Participation

FOSDEM 2017 Electronic Design Automation Devroom
Call for Participation

This is the call for participation in the FOSDEM 2017 devroom on Free/Open Source Software (FOSS) Electronic Design Automation (EDA) tools, to be held on Sunday 5 February 2017 in Brussels, Belgium. We are looking for contributions under the form of talks and tutorials covering the following main topics:

• Printed Circuit Board (PCB) design tools (e.g. KiCad and gEDA)
• Analogue and digital simulators (e.g. ngspice, Qucs, Gnucap, Xyce, GHDL, Icarus and Verilator)
• Any other EDA tools such as high-level tools for digital hardware design (e.g. Migen) and HDL synthesis tools (e.g.Yosys)
• Inter-project opportunities for collaboration

We hope to provide an opportunity for attendees to bring themselves up to date on the latest FOSS EDA developments, share knowledge and identify opportunities to collaborate on development tasks. Have a look at last year's event for a taste of what the EDA devroom is about.

The submission process
Please submit your proposals at 

https://penta.fosdem.org/submission/FOSDEM17 

before 1 December 2016.

If you already have a Pentabarf account (for example as a result of having submitted a proposal in the past), make sure you use it to log in and submit your proposal. Do not create a new account if you already have one. Please provide a bit of information about yourself under Person -> Description -> Abstract. When you submit your proposal (creating an "Event" in Pentabarf), make sure you choose the "Electronic Design Automation (EDA) devroom" in the track drop-down menu. Otherwise your proposal might go unnoticed. Fill in at least a title and abstract for the proposed talk and a suggested duration. Bear in mind that a lot of the value in these meetings comes from the discussions, so please be reasonable regarding the duration of the talk.

Important dates

• 1 December 2016: deadline for submission of proposals
• 11 December 2016: announcement of final schedule
• 5 February 2017: devroom day

Recordings
The FOSDEM organisers hope to be able to live-stream and record all the talks. The recordings will be published under the same licence as all FOSDEM content (CC-BY). Only presentations will be recorded, not informal discussions and whatever happens during the lunch break. By agreeing to present at FOSDEM, you automatically give permission to be recorded. The organisers will agree to make exceptions but only for exceptional and well-reasoned cases.
Mailing list

Feel free to subscribe to the mailing list of the EDA devroom to submit ideas, ask questions and generally discuss about the event.

Spread the word!
This is the third EDA devroom at FOSDEM. The first two were very well received. Let's make sure as many projects and developers as possible are present. Thanks!

[mos-ak] A new approach to compact semiconductor device modelling with Qucs Verilog-A analogue module synthesis

A new approach to compact semiconductor device modelling with Qucs Verilog-A analogue module synthesis  

M. E. Brinson 1,* andV. Kuznetsov 2  

Keywords:Qucs; Verilog-A analogue module synthesis;equation-defined devices (EDD); compact device modelling; circuit simulation  

Summary: Since the introduction of SPICE non-linear controlled voltage and current sources, they have become a central feature in the interactive development of behavioural device models and circuit macromodels. The current generation of SPICE-based open source general public license circuit simulators, including Qucs, Ngspice and Xyce©, implements a range of mathematical operators and functions for modelling physical phenomena and system performance. The Qucs equation-defined device is an extension of the SPICE style non-linear B type controlled source which adds dynamic charge properties to behavioural sources, allowing for example, voltage and current dependent capacitance to be easily modelled. Following, the standardization of Verilog-A, it has become a preferred hardware description language where analogue models are written in a netlist format combined with more general computer programming features for sequencing and controlling model operation. In traditional circuit simulation, the generation of a Verilog-A model from a schematic, with embedded non-linear behavioural sources, is not automatic but is normally undertaken manually. This paper introduces a new approach to the generation of Verilog-A compact device models from Qucs circuit schematics using a purpose built analogue module synthesizer. To illustrate the properties and use of the Qucs Verilog-A module synthesiser, the text includes a number of semiconductor device modelling examples and in some cases compares their simulation performance with conventional behavioural device models. Copyright © 2016 John Wiley & Sons, Ltd.  

Article first published online: 15 APR 2016; DOI: 10.1002/jnm.2166  

References
[1] Newton AR, Pederson DO, Sangiovanni-Vincentelli A. SPICE Version 2g User's Guide. Department of Electrical Engineering and Computer Sciences, University of California: Berkeley, CA, 1981.
Go here for SFX
[2] Johnson B, Quarles T, Newton AR, Pederson DO, Sangiovanni-Vincentelli A. Berkeley, CA. Department of Electrical Engineering and Computer Sciences, University of California, 1992.
Go here for SFX
[3] Brinson M, Crozier R, Kuznetsov V, Novak C, Roucaries B, Schreuder F, Torri GT. Qucs (Quite universal circuit simulator), 2015. Available from: http;//qucs.sourceforge.net [Accessed November 2015].
[4] Nenzi P, Vogt H. Ngspice-26 (Next generation SPICE version 26), 2015. Available from: http://ngspice.sourceforge. net. [Accessed November 2015].
[5] Sandia National Laboratories, US, Xyce parallel electronic simulator version 6.3., 2015. Available from: http: //xyce.sandia.gov.[Accessed November 2015].
[6] Jahn S, Brinson ME. Interactive compact device modelling using Qucs equation-defined devices. International Journal of Numerical Modelling: Electronic Networks, Devices and Fields 2008; 21(5): 335–349.
Direct Link:
Abstract PDF(1011K) References Web of Science® Times Cited: 7 Go here for SFX
[7] Brinson ME, Jahn S. Qucs: a GPL software package for circuit simulation, compact device modelling and circuit macromodelling from DC to RF and beyond. International Journal of Numerical Modelling: Electronic Networks, Devices and Fields 2009; 22(4): 297–319.
Direct Link:
Abstract PDF(1156K) References Web of Science® Times Cited: 7 Go here for SFX
[8] Accellera, Verilog-AMS Language Reference Manual. Version 2.3.1., 2009. Available from: http://www.accellera.org. [Accessed November 2015.]
[9] Silicon Integration Initiative (Si2), Compact Model Coalition, 2015. Available from: http;//www.si2.org. [Accessed November 2015.]
[10] Brinson ME, Jahn S. Modelling high-frequency inductance with Qucs non-linear radio frequency equation defined devices.International Journal of Electronics 2009; 96(3): 307–321.
CrossRef, Web of Science® Times Cited: 1
Go here for SFX
[11] Lemaitre L, Gu B. ADMS - A fully Customizable Compact Model Compiler, NSTI-Nanotech, 2008. Available from: www.nsti.org[Accessed March 2016].
Go here for SFX
[12] Lemaitre L, Grabinski W, McAndrew C. Compact device modelling using Verilog-AMS and AMS. Electron Technology (Internet Journal). June 6 2003, pp 1-5. Available from: http://www.ite.waw.pl/etij/pdf/35-03p.pdf. [Accessed November 2015.]
[13] Lemaitre L, McAndrew CM, Hamm S. Automatic Device Model Synthesis. CICC: Florida, USA, 2002.
Go here for SFX
[14] Eaton JW. GNU Octave. Version 4.0, 2015. Available from: https:www.gnu.org/software/octave/. [Accessed November 2015.]
[15] Brinson M, Crozier R, Novak C, Roucaries B, Schreuder F, Torri GT. Building a second generation Qucs GPL circuit simulator: package structure, simulation features and compact device modelling capabilities. London, 2014. Available from: http://www.mos-ak.org/london−2014/presentations/09−Mike−Brinson−MOS-AK−London−2014.pdf. [Accessed November 2015].
Go here for SFX
[16] Brinson M, Crozier R, Kuznetsov V, Novak C, Roucaries B, Schreuder F, Torri GT. Qucs: an introduction to the new simulation and compact device modelling features implemented in release 0.0.19/0.0.19Src2 of the popular GPL circuit simulator. MOS-AK ESSDERC/ESSCIRC Workshop. 18 September Graz, Austria 2015. Available from: http://www.mos-ak.org/graz−2015/presentationsT−5−Brinson−MOS-AK−Graz−2015.pdf. [Accessed November 2015].
Go here for SFX
[17] Anognetti P, Massobrio G. Semiconductor Device Modeling with SPICE. McGraw-Hill Inc: New York, 1988.
Go here for SFX
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[Call for Participation] FOSDEM 2016 Electronic Design Automation Devroom

 Call for Participation 

FOSDEM 2016 Electronic Design Automation Devroom 

This is the call for participation in the FOSDEM 2016 devroom on Free/Open Source Software (FOSS) Electronic Design Automation (EDA) tools, to be held on Saturday 30 January 2016 in Brussels, Belgium. We are looking for contributions under the form of talks covering the following main topics:

• Printed Circuit Board (PCB) design tools (e.g. KiCad and gEDA)
• Analogue and digital simulators (e.g. ngspice, Qucs, Gnucap, Xyce, GHDL, Icarus and Verilator)
• Any other EDA tools such as high-level tools for digital hardware design (e.g. Migen)
• Inter-project opportunities for collaboration

We hope to provide an opportunity for attendees to bring themselves up to date on the latest FOSS EDA developments, share knowledge and identify opportunities to collaborate on development tasks. Have a look at last year's event for a taste of what the EDA devroom is about.

The submission process
Please submit your proposals at https://penta.fosdem.org/submission/FOSDEM16 

before 4 December 2015.

If you already have a Pentabarf account (for example as a result of having submitted a proposal in the past), make sure you use it to log in and submit your proposal. Do not create a new account if you already have one. Please provide a bit of information about yourself under Person -> Description -> Abstract. When you submit your proposal (creating an "Event" in Pentabarf), make sure you choose the "EDA devroom" in the track drop-down menu. Otherwise your proposal might go unnoticed. Fill in at least a title and abstract for the proposed talk and a suggested duration. Bear in mind that a lot of the value in these meetings comes from the discussions, so please be reasonable regarding the duration of the talk.

Important dates

• 4 December 2015: deadline for submission of proposals
• 18 December 2015: announcement of final schedule
• 30 January 2016: devroom day

[Read More]

Octave-Forge Community Choice POTM

The Octave-Forge packages -- Community Choice Project of the Month for July

For one of the July "Community Choice" Projects of the Month, the community elected Octave-Forge, a central location for the collaborative development of packages for GNU Octave, a high-level interpreted language. The Octave-Forge packages expand Octave's core functionality by providing field specific features via Octave's package system. Some of the individual Octave-Forge packages include: image and signal processing, fuzzy logic, instrument control, and statistics packages.

Download Octave-Forge now.

Related Projects:

• VFreeMat--An interpreted, matrix-oriented development environment for engineering and scientific applications.
• AquaTerm--A Mac OS X grahics renderer.
• Quite Universal Circuit Simulator--A circuit simulator with graphical user interface (GUI)

QUCS: Project of the Week, June 1, 2015

 The Qucs is one of the featured projects for the week (June 1, 2015), which appear on the front page of SourceForge.net:

 Qucs is a circuit simulator with a graphical user interface. The software aims to support all kinds of circuit simulation types such as, e.g. DC, AC, S-parameter, Transient, Noise, and Harmonic Balance analysis. Pure digital simulations are also supported.
[ Download Quite Universal Circuit Simulator ]

QucsStudio 1.4.2

A new version of QucsStudio has just been released for general use. The latest version is mainly  bug fixes but does contain a number of new/improved features. A list of the changes are given below:

• some corrections in help system
• component names in noise contribution analysis with subcircuit prefix
• reduced time step warnings in transient analysis
• bugfix: differential voltages in equations
• in equations: allow suffix in node names
• bugfix: directory MinGW\mingw32\bin\ exists again
• bugfix: crash in diagram dialog if clicking on empty variable area
• new component: photodiode
• new equation function: stoa()
• bugfix: spaces allowed between function name and "("
• added InP permittivity in property list
• bugfix: correct text in C++ symbol string
• error message for wrong index in equation variables

This is likely to be one of the last releases in the QucsStudio 1.4 series.  Work has started on QucsStudio series 2.0.0.  QucsStudio 2.0.0 is expected to offer users significant improvements in simulation and modelling capabilities.  The first of the new releases will coincide with the tenth anniversary of the first release of Qucs next year.

QucsStudio can be downloaded from the QucsStudio homepage at http://www.mydarc.de/DD6UM/QucsStudio/qucsstudio.html

Contact: Mike Brinson