[paper] TFT for Mixed Signal and Analog Computation

Eva Bestelink, Olivier de Sagazan, Lea Motte, Max Bateson, Benedikt Schultes, S. Ravi P. Silva,

and Radu A. Sporea

Versatile Thin‐Film Transistor with Independent Control of Charge Injection and Transport

for Mixed Signal and Analog Computation

Adv. Intell. Syst.. (2020) pp.1-9, DOI:10.1002/aisy.202000199 

Abstract: New materials and optimized fabrication techniques have led to steady evolution in large area electronics, yet significant advances come only with new approaches to fundamental device design. The multimodal thin-film transistor introduced here offers broad functionality resulting from separate control of charge injection and transport, essentially using distinct regions of the active material layer for two complementary device functions, and is material agnostic. The initial implementation uses mature processes to focus on the device’s fundamental benefits. A tenfold increase in switching speed, linear input–output dependence, and tolerance to process variations enable low-distortion amplifiers and signal converters with reduced complexity. Floating gate designs eliminate deleterious drain voltage coupling for superior analog memory or computing. This versatile device introduces major new opportunities for thin-film technologies, including compact circuits for integrated processing at the edge and energy-efficient analog computation.

Figure: Outcomes of separating control for injection and conduction shown via TCAD simulation. a) MMT transient response is much faster than conventional contact-controlled TFTs

b) A MMT with multiple, appropriately sized CG1 gates can function as a digital-to-analog converter (DAC) with CG2 providing an enabling, sampleand-hold (S/H) function. 

Acknowledgements: E.B. and R.A.S. contributed equally to this work. This work was partly supported through EPSRC grants EP/R511791/1 and EP/R028559/1 and Research Fellowship 10216/110 from the Royal Academy of Engineering of Great Britain. Device fabrication had been performed on the NanoRennes platform. The authors thank Dr. Brice Le Borgne for initial liaison and process discussions, Prof. John M. Shannon for on-going advisory meetings, Prof. Craig Underwood for reviewing the manuscript, Dr. David Cox and Mr. Mateus Gallucci Masteghin for assistance with the SEM images.

[paper] Flexible MO TFT for Analog Applications

Giuseppe Cantarella¹, Júlio Costa², Tilo Meister³, Koichi Ishida³, Corrado Carta³, Frank Ellinger³, Paolo Lugli¹, Niko Münzenrieder^1,2 and Luisa Petti¹

Review of recent trends in flexible metal oxide thin-film transistors for analog applications

Flexible and Printed Electronics 2020, Vol. 5, No. 3

DOI: 10.1088/2058-8585/aba79a

¹Faculty of Science and Technology, Free University of Bozen-Bolzano, 39100, Bozen, Italy
²Flexible Electronics Laboratory, University of Sussex, Brighton, BN1 9QT, United Kingdom
³Chair of Circuit Design and Network Theory, TU Dresden, 01069 Dresden, Germany

Abstract: Thanks to the extraordinary advances flexible electronics have experienced over the last decades, applications such as conformable active-matrix displays, ubiquitously integrated disposable flexible sensor nodes, wearable or textile-integrated systems, as well as imperceptible and transient implants are now reachable. To enable these applications, specialized analog circuits able to transmit and receive data, condition sensors' parameters, drive actuators or control powering devices are required. High-performance sensor conditioning, driving and transceiver circuits on a wide range of flexible substrates are therefore extremely important to develop. However, the currently available materials and processes compatible with mechanically flexible substrates impose massive limitations in terms of large-area uniformity, device dimensions' shrinkability and circuit design, challenging the realization of flexible analog systems. Among state-of-the-art technologies employing low-temperature fabrication processes, thin-film transistors (TFTs) based on metal oxide semiconductors represent the potentially best compromise in terms of prize, performance, technology maturity and capacity to realize complex systems. This is why metal oxide TFTs are nowadays widely used for flexible, light-weight, transparent, stretchable and bio-degradable analog circuits and systems. Here, we review the current trends of flexible metal oxide TFTs for analog applications. First, an introduction is given, where current challenges and requirements related to the realization of flexible analog circuits and systems are analysed. Additionally, TFT performance parameters and configurations are briefly revised. Then, the recent advances in the field of flexible metal oxide TFTs for analog applications are summarized. In particular, all reported approaches to reduce the channel length and improve the AC performance are shown. Next, the current state of flexible metal oxide TFT-based analog circuits is shown, discussing n-type only and complementary circuit configurations. The last topic of the review covers systems based on flexible metal oxide analog circuits. Finally, a conclusion is drawn and an outlook over the field is provided.

Figure: Overview of published works on flexible metal oxide TFT based circuits, indicating the minimum channel length of the devices, the operation frequency of the circuits, the effective supply voltage used, as well as the total TFT count. Only integrated circuits are included.

Acknowledgments: This work was partially supported by the DFG FFlexCom Priority Programme, Germany, through projects WISDOM II and Coordination Funds, under Grants 271795180 and 270774198. This work was also partially funded with internal funding of the Faculty of Science and Technology of the Free University of Bolzano-Bozen (project ”EYRE” RTD Call 2019).

An Empirical Model to Enhance the Flexibility of gm/Id Tuning in BSIM-BULK Model

Ravi Goel, Chetan Gupta, Yogesh S. Chauhan

EE Department, Indian Institute of Technology Kanpur, Kanpur, India

Published in: 2018 5th IEEE Uttar Pradesh Section International Conference on Electrical, Electronics and Computer Engineering (UPCON)

Abstract: Recent enhancement in BSIM-BULK (formerly BSIM6) model is presented in this work. The industry standard models like BSIM4, PSP, BSIM-BULK etc. lack the parameters for tuning of transconductance to channel current ratio (gm/Id). gm/Id is also a critical figure of merit for analog applications. Here, we propose an empirical model to enhance the flexibility of gm/Id tuning behavior. The proposed model provides good fitting for different channel lengths and drain bias.

Paper Sections:
I. Introduction
II. An Empirical Model for gm/Id Tuning
III. Model Implementation
IV. Model Validation with TCAD
V. Conclusion

Source:
DOI: 10.1109/UPCON.2018.8597065

Digital and analog TFET circuits: Design and benchmark

Solid-State Electronics
Volume 146, August 2018, Pages 50–65
Invited Review

S. Strangio^a,b, F. Settino^a,b, P. Palestri^a, M. Lanuzza^b, F. Crupi^b, D. Esseni^a, L. Selmi^a,c

^aDPIA, Università degli Studi di Udine, Via delle Scienze 206, I-33100 Udine, UD, Italy
^bDIMES, Università della Calabria, Via P. Bucci, 41C, I-87036 Arcavacata di Rende (CS), Italy
^cDipartimento di Ingegneria “Enzo Ferrari”, Università degli Studi di Modena e Reggio Emilia, I-41100 Modena, Italy

ARTICLE INFO: The review of this paper was arranged by Prof. S. Cristoloveanu
https://doi.org/10.1016/j.sse.2018.05.003

HIGHLIGHTS:

• We report simulations of basic analog and digital circuit blocks employing tunnel-FETs.
• Template III-V heterojunction tunnel-FETs are benchmarked against silicon FinFETs for the 10 nm node.
• Performance are evaluated down to VDD = 200 mV.
• Tunnel-FETs result advantageous with respect to silicon FinFET for VDD below approximately 400 mV.

ABSTRACT: In this work, we investigate by means of simulations the performance of basic digital, analog, and mixed-signal circuits employing tunnel-FETs (TFETs). The analysis reviews and complements our previous papers on these topics. By considering the same devices for all the analysis, we are able to draw consistent conclusions for a wide variety of circuits. A virtual complementary TFET technology consisting of III-V heterojunction nanowires is considered. Technology Computer Aided Design (TCAD) models are calibrated against the results of advanced full-quantum simulation tools and then used to generate look-up-tables suited for circuit simulations. The virtual complementary TFET technology is benchmarked against predictive technology models (PTM) of complementary silicon FinFETs for the 10nm node over a wide range of supply voltages (VDD) in the sub-threshold voltage domain considering the same footprint between the vertical TFETs and the lateral FinFETs and the same static power. In spite of the asymmetry between p- and n-type transistors, the results show clear advantages of TFET technology over FinFET for VDD lower than 0.4V. Moreover, we highlight how differences in the I-V characteristics of FinFETs and TFETs suggest to adapt the circuit topologies used to implement basic digital and analog blocks with respect to the most common CMOS solutions.

FIG: Sketch of n- and p-type TFET and FinFET device architectures. The red and blue colors indicate the n- and p-doping types, respectively (green: intrinsic semiconductor, transparent-grey: oxide). TFET dimensions are: LG=20nm, nanowire cross section (LS)=7nm, EOT=1nm. FinFET dimensions are: LG=14nm, tfin=8nm, hfin=21nm, EOT=0.88nm. (For interpretation of the references to colour in this figure legend, the reader is referred to the web version of this article.)