Showing posts with label Integrated circuit. Show all posts
Showing posts with label Integrated circuit. Show all posts

Mar 25, 2026

[Open Source Survey] From RTL to Fabrication

Emilio Isaac Baungarten-Leon
From RTL to Fabrication: Survey of Open-Source EDA Tools and PDKs
Electronics 2026, 15(5), 1048;
DOI: 10.3390/electronics15051048

* Departamento de Electromecánica, Universidad Autónoma de Guadalajara, Zapopan 45129, Mexico


Abstract: This article aims to synthesize the current ecosystem of open-source tools for Integrated Circuit (IC) design, covering the entire digital design flow from Register-Transfer Level (RTL) description to fabricable layouts. The survey categorizes and analyzes tools across major stages of design, including code-generation tools, logic synthesis, simulation, and physical design flow. Special emphasis is given to the fabricable open-source Process Design Kit (PDK), which enables the physical realization of open-hardware projects. By examining interoperability, limitations, and maturity across this toolchain, the article provides a comprehensive overview of the Electronic Design Automation (EDA) landscape and identifies the research and educational opportunities that arise from democratizing silicon design through open and reproducible workflows.
Fig: (a) IC design flow illustrating the complete process from RTL specification through logic synthesis, physical design (floorplanning, placement, clock tree synthesis, routing), verification, and final GDSII generation for fabrication. (b) FPGA design flow showing the progression from RTL description to synthesis, technology mapping, placement-and-routing on the target FPGA fabric, bitstream generation, and device configuration.

Acknowledgments: The APC was funded by Universidad Autónoma de Guadalajara (UAG), financial support provided through its Fondo Semilla. The author gratefully acknowledges the Universidad Autónoma de Guadalajara (UAG) for the financial support provided through its Fondo Semilla program, which covered the article processing charges and enabled the publication of this work. During the preparation of this manuscript, the authors utilized GPT-5.2 solely to enhance the clarity, grammar, and overall quality of the English text. The author reviewed and edited all AI-assisted content and takes full responsibility for the accuracy, originality, and integrity of the final manuscript.

Table A1. Main open-source EDA tools and their official repositories
Category Tool Official Link
Code-Generation ToolsPandA Bambu HLShttps://github.com/ferrandi/PandA-bambu (accessed on 20 January 2026)
Kiwi Compilerhttps://www.cl.cam.ac.uk/~djg11/kiwi/ (accessed on 20 January 2026)
LegUp HLShttps://github.com/LegUpComputing/legup-examples?tab=readme-ov-file (accessed on 20 January 2026)
ROCCChttp://roccc.cs.ucr.edu/ (accessed on 20 January 2026)
PyMTL3https://github.com/pymtl/pymtl3 (accessed on 20 January 2026)
Chiselhttps://www.chisel-lang.org/ (accessed on 20 January 2026)
SpinalHDLhttps://github.com/SpinalHDL/SpinalHDL (accessed on 20 January 2026)
Pyveriloghttps://github.com/PyHDI/Pyverilog (accessed on 20 January 2026)
Amaranth HDLhttps://github.com/amaranth-lang (accessed on 20 January 2026)
LLM-Based Code GenerationRTLCoderhttps://github.com/hkust-zhiyao/RTL-Coder (accessed on 20 January 2026)
Spec2RTL-Agenthttps://cirkitly.kernex.sbs/ (accessed on 20 January 2026)
OriGenhttps://github.com/pku-liang/OriGen (accessed on 20 January 2026)
AutoChiphttps://github.com/shailja-thakur/AutoChip (accessed on 20 January 2026)
CodeVhttps://github.com/cluesmith/codev (accessed on 20 January 2026)
VeriCoderhttps://github.com/Anjiang-Wei/VeriCoder (accessed on 20 January 2026)
StarCoderhttps://github.com/bigcode-project/starcoder (accessed on 20 January 2026)
CodeLlamahttps://github.com/meta-llama/codellama (accessed on 20 January 2026)
DeepSeek-Coderhttps://github.com/deepseek-ai/DeepSeek-Coder (accessed on 20 January 2026)
CodeQwenhttps://github.com/QwenLM/qwen-code (accessed on 20 January 2026)
Geminihttps://gemini.google.com/ (accessed on 20 January 2026)
GPThttps://chatgpt.com/ (accessed on 20 January 2026)
ChatEDAhttps://github.com/wuhy68/ChatEDA (accessed on 20 January 2026)
Synthesis ToolsYosyshttps://yosyshq.net/yosys/ (accessed on 20 January 2026)
ABC (Berkeley)https://people.eecs.berkeley.edu/~alanmi/abc/ (accessed on 20 January 2026)
ODIN II (VTR)https://docs.verilogtorouting.org/en/latest/odin/ (accessed on 20 January 2026)
GHDL-Yosys Pluginhttps://github.com/YosysHQ/yosys (accessed on 20 January 2026)
Synlighttps://github.com/chipsalliance/synlig (accessed on 20 January 2026)
Mockturtle (EPFL)https://github.com/lsils/mockturtle (accessed on 20 January 2026)
Simulation & Verification ToolsVerilatorhttps://www.veripool.org/verilator/ (accessed on 20 January 2026)
Icarus Veriloghttps://steveicarus.github.io/iverilog/ (accessed on 20 January 2026)
cocotbhttps://www.cocotb.org/ (accessed on 20 January 2026)
GTKWavehttps://gtkwave.sourceforge.net/ (accessed on 20 January 2026)
Yosys-SMTBMChttps://symbiyosys.readthedocs.io/en/latest/reference.html (accessed on 20 January 2026)
EQYhttps://github.com/YosysHQ/eqy (accessed on 20 January 2026)
CoSAhttps://github.com/cristian-mattarei/CoSA (accessed on 20 January 2026)
OpenSTAhttps://github.com/The-OpenROAD-Project/OpenSTA (accessed on 20 January 2026)
OpenTimerhttps://github.com/OpenTimer/OpenTimer (accessed on 20 January 2026)
Tatum (VTR)https://github.com/verilog-to-routing/tatum (accessed on 20 January 2026)
Physical Design Flow ToolsOpenROADhttps://theopenroadproject.org/ (accessed on 20 January 2026)
OpenLanehttps://github.com/The-OpenROAD-Project/OpenLane (accessed on 20 January 2026)
iEDAhttps://github.com/OSCC-Project/iEDA (accessed on 20 January 2026)
SiliconComphttps://github.com/siliconcompiler/siliconcompiler (accessed on 20 January 2026)
Fabricable PDKsSKY130https://github.com/gdsfactory/skywater130 (accessed on 20 January 2026)
GF180MCUhttps://github.com/google/gf180mcu-pdk (accessed on 20 January 2026)
IHP SG13G2https://github.com/IHP-GmbH/IHP-Open-PDK (accessed on 20 January 2026)
ICsprout55https://github.com/openecos-projects/icsprout55-pdk (accessed on 20 January 2026)

Jan 18, 2024

[paper] Open-source design of integrated circuits

Patrick Fath, Manuel Moser, Georg Zachl. Harald Pret
Open-source design of integrated circuits
Elektrotech. Inftech. (2024)
DOI: 10.1007/s00502-023-01195-5

* Institute for Integrated Circuits, Johannes Kepler University Linz, Austria

Abstract: This paper presents the design of a self-clocked 12-bit non-binary fully differential SAR-ADC using the SKY130 open-source PDK. The entire mixed-signal circuit design and layout were created with free and open-source software. The ADC reaches a sample rate of up to 1.44MS/s at 1.8V supply while consuming 703μW of power on a small 0.175mm area. A configurable decimation filter can increase the ADC resolution up to 16 bits while using an oversampling factor of 256. A 9‑bit thermometer-coded and 3‑bit binary-coded DAC matrix using a 448 aF waffle-capacitor results in a total capacitance of 1.83pF per input. Realizations of configurable analog functions using the form factor of SKY130 high-density standard cells allow the parametrization of an analog circuit in a hardware description language and hardening of the macro in an intentionally digital workflow.
FIG: Block diagram of the proposed open-source design flow,
including the essential tools and used/generated files

Acknowledgements: The authors thank Johannes Kepler University for funding the open-access publication, Google and SkyWater Technologies for igniting this recent wave of open-source IC design, and the large crowd of enthusiasts spending their time on developing and maintaining an extensive array of exciting open-source EDA projects. Open access funding provided by Johannes Kepler University, Linz.