[paper] 1.5-nm Node SGT SRAM Cell

[paper] 1.5-nm Node Surrounding Gate Transistor (SGT)-SRAM Cell with Staggered Pillar and Self-Aligned Process for Gate, Bottom Contact, and Pillar“ will be presented by Yisuo Li at virtual IMW on May 21st, 10:20am // Global TCAD Solutions https://t.co/cr2rvkpXij #semi pic.twitter.com/TSXSO5Db6l

— Wladek Grabinski (@wladek60) May 7, 2021

---

from Twitter https://twitter.com/wladek60

May 07, 2021 at 11:52AM
via IFTTT