IEEE SSCS PICO Contestants Cross the Finish Line

by Boris Murmann

DOI:10.1109/MSSC.2021.3135176

Date of current version: 24 January 2022

Last summer 2021, the IEEE Solid-State Circuits Society (SSCS) launched its first open source chip design contest under the umbrella of its Platform for Integrated Circuit Design Outreach program (PICO). Beginning with 61 submissions, a volunteer jury selected 18 teams from nine countries to embark on a journey toward tapeout. Anyone interested in supporting future activities is encouraged to sign up at the Society’s volunteer web portal. Stay tuned for the 2022 edition of the SSCS PICO contest!

FIG: Layout views of the chips submitted for tape out

      TABLE: A Summary Oof Designs Submitted for TapeOut

	Function	Team	Chip URL
1	5G bidirectional amplifier	Pakistan 3 (National University of Computer and Emerging Sciences)	https://efabless.com/projects/560
2	Wireless power transfer unit	Pakistan 2 (National University of Computer and Emerging Sciences)
3	Variable precision fused multiply–add unit	Pakistan 1 (National University of Computer and Emerging Sciences)
4	Oscillator-based LVDT readout	India 2 (Anna University)	https://efabless.com/projects/474
5	Temperature sensor	India 1 (Anna University)
6	GPS baseband engine	India 3 (Anna University)
7	Ultralow-power analog front end for bio signals	Brazil 2 (Universidade Federal de Santa Catarina)	https://efabless.com/projects/476
8	TIA for quantum photonics interface	USA 4 (University of Virginia)	https://efabless.com/projects/470
9	Bandgap reference	Egypt (Cairo University)	https://efabless.com/projects/473
10	Neural network for sleep apnea detection	USA 2 (University of Missouri)
11	Sonar processing unit	Chile (University of the Bío-Bío)	https://efabless.com/projects/54

Circuit Design and Simulation Marathon using eSIM

 

Indian Institute of Technology, Bombay

We are happy to announce the first ever #Circuit #Design and #Simulation #Marathon using #eSim! This event is jointly organized by #FOSSEE and VLSI System Design. The FOSSEE project developed at Indian Institute of Technology, Bombay is powered by MINISTRY OF EDUCATION, GOVERNMENT OF INDIA.

To know more about the Circuit Design and Simulation Marathon, please visit https://hackathon.fossee.in/esim/

Important dates:
>> Registration: 21 May 2021 - 15 June 2021
>> Marathon Launch : 17 June 2021