[VIRTUAL] EDS MQ on Compact Modeling

VIRTUAL MINI-COLLOQUIUM ON COMPACT MODELING

IEEE EDS Compact Modeling Technical Committee

EDS Spain Chapter

Department of Electronic, Electrical and Automatic Control Engineering, 

University Rovira I Virgili, Tarragona (Spain)

December 17, 2020 EDS MQ Program (times in CET)
	10:20-10:30 Benjamin Iñiguez, IEEE EDS MQ Chair Department of Electronic, Electrical and Automatic Control Engineering, University Rovira I Virgili, Tarragona (Spain) Opening session
	10:30-11:15 Yogesh. S Chauhan Department of Electrical Engineering, Indian Institute of Technology Kanpur (India) “BSIM-BULK and BSIM-HV: Industry Standard SPICE Models for Analog, RFand High Voltage Applications”
	11:15-12:00 Manoj Saxena Department of Electronics, University of Delhi  (India) “Modeling and Simulation of Robust Ultrasensitive Tunnel Field Effect Transistor Design for Biosensing Applications”
	12·00-12:45 Wladek Grabinski GMC, Commugny (Switzerland) “FOSS TCAD/EDA Tools for Semiconductor Device Modeling”
	12:45-13:30 Arokia Nathan Darwin College, University of Cambridge (UK) “Physics-Based Parameter Extraction for TFTs”
	13:30-15:00 Break
	15:00-15:45 Marcelo Pavanello Department of Electrical Engineering, Centro Universitario FEI, Sao Bernardo do Campo (Brazil) "Quantum Effects on the Mobility of SOI Nanowire MOSFETs Induced by the Active Substrate Bias"
	15:45-16:30 Michael S. Shur Department of Electrical, Systems and Computer Engineering, Rensselaer Polytechnic Institute, Troy NY (USA) “THz Compact SPICE/ADS model”
	16:30-17:15 Edmundo Gutiérrez Department of Electronics, INAOE, Puebla (Mexico) "RF MOSFET degradation modeling up to 67 GHz”
	End of EDS MQ

[Foreword] Special Issue on Compact Modeling of Semiconductor Devices

Foreword

Special Issue on Compact Modeling of Semiconductor Devices

DOI: 10.1109/JEDS.2020.3039023

THIS Special Issue is dedicated to recent research in the field of compact modeling of semiconductor devices. This is the first J-EDS Special Issue on compact modeling. In the last years, a number of new semiconductor device structures, for electronic and photonic applications, have been developed. Compact models are needed for the incorporation of these new devices in integrated circuits. Therefore, a Special Issue was needed to present recent compact modeling solutions for semiconductor devices

A total of 8 regular papers and 2 invited papers have been accepted in this Special Issue. All papers, including the invited ones, were subjected to a thorough peer reviewing. A high number of reviewers participated in this process. This has resulted in a Special Issue containing very high-quality papers.  The published papers target compact modeling aspects for a wide number of devices, such as SiGe HBTs, IGBTs, SiC SB diodes, LDMOSFETs, Multi-Gate MOSFETs, RRAMs, TFET SRAMs, and organic TFTs. Open source Verilog-A compil- ing is also targeted by one paper. Different operation regimes and conditions are addressed: charging/discharging, THz, high power, tunneling radiation environments, . . . 

One invited paper, by U. Sharma and S. Mahapatra, addresses the modeling of HCD Kinetics for full VG/VD span under different experimental conditions across architectures and its SPICE implementation The other invited paper, by Fregonese et al., presents a review of THz characterization and modeling of SiGE HBTs.

I [BJ] would like to thank the work done by the rest of the Editors of this Special Issue and also by all the reviewers who participated in this process. And of course, I want to thank all the authors for their interest in submitting papers to this Special Issue. Thanks to authors, reviewers, and editors, this high-quality Special Issue has been possible.

BENJAMIN IÑIGUEZ, Guest Editor-in-Chief Department of Electronic, Electrical and Automatic Control Engineering University Rovira i Virgili 43007 Catalonia, Spain YOGESH SINGH CHAUHAN, Guest Associate Editor Department of Electrical Engineering Indian Institute of Technology Kanpur Kanpur 208016, India SLOBODAN MIJALKOVIC, Guest Associate Editor Simulation Group EDA Division Silvaco Europe Ltd. Cambridgeshire PE27 5JL, U.K. KEJUN XIA, Guest Associate Editor Department of Front End Innovation NXP Semiconductors Chandler, AZ 85224 USA

JUNG-SUK GOO, Guest Associate Editor Department of Compact Model Development GLOBALFOUNDRIES Inc. Santa Clara, CA 95054 USA MARCELO PAVANELLO, Guest Associate Editor Department of Electrical Engineering Centro Universitario FEI 09850-901 São Bernardo do Campo, Brazil MAREK MIERZWINSKI, Guest Associate Editor Department of PathWave Software and Solutions Keysight Technologies Santa Rosa, CA 95403 USA (e-mail: ) WLADEK GRABINSKI, Guest Associate Editor Department of Research and Development Modelling GMC Consulting 1291 Commugny, Switzerland

[paper] THz characterization and modeling of SiGe HBTs

Sebastien Fregonese, Marina Deng, IEEE member, Marco Cabbia, Chandan Yadav*, IEEE member, Magali De Matos, and Thomas Zimmer, Senior Member, IEEE

THz characterization and modeling of SiGe HBTs

review (invited)

IEEE J-EDS, 2020, pp.1-1 

DOI:10.1109/JEDS.2020.3036135

hal-03014869

IMS Laboratory, University of Bordeaux (F)
*Department of Electronics and Communication Engineering, National Institute of Technology Calicut (IN)

Abstract: This paper presents a state-of-art review of on-wafer S-parameter characterization of THz silicon transistors for compact modelling purpose. After, a brief review of calibration/deembedding techniques, the paper focuses on the on-wafer calibration techniques and especially on the design and dimensions of lines built on advanced silicon technologies. Other information such as the pad geometry, the ground plane and the floorplan of the devices under test are also compared. The influence of RF probe geometry on the coupling with the substrate and adjacent structures is also considered to evaluate the accuracy of the measurement, especially using EM simulation methodology. Finally, the importance of measuring above 110 GHz is demonstrated for SiGe HBT parameter extraction. The validation of the compact model is confirmed thanks to an EM-spice cosimulation that integrates the whole calibration cum deembedding procedure.

Fig: EM probe models based on Picoprobe GGB (a) 1 GHz -110 GHz, (b) WR5, (c) WR3 and d) WR2.2. In all models, white=coaxial insulator, gray=solder, yellow=metal.

A complete description of probe topology and technology is given in:

A. Rumiantsev et R. Doerner; RF Probe Technology: History and Selected Topics; IEEE Microw. Mag., vol. 14, no 7, p. 46‑58, Nov. 2013, DOI: 10.1109/MMM.2013.2280241

Aknowledgement: This work is partly funded by the French Nouvelle-Aquitaine Authorities through the FAST project. The authors also acknowledge financial support from the EU under Project Taranto (No. 737454). The authors would like to thank STM for supplying the silicon wafer.

[paper] Compact Modeling of Organic TFT

Jakob Pruefer, Jakob Leise, Ghader Darbandy, Aristeidis Nikolaou, Hagen Klauk, James W. Borchert, Benjamín Iñíguez, Fellow, IEEE, Thomas Gneiting, Member, IEEE

and Alexander Kloes, Senior Member, IEEE

Compact Modeling of Short-Channel Effects in Staggered Organic Thin-Film Transistors

IEEE Transactions on Electron Devices, vol. 67, no. 11, pp. 5082-5090, Nov. 2020

DOI: 10.1109/TED.2020.3021368.

Abstract:This article introduces analytical compact models of short-channel effects in staggered organic thinfilm transistors (TFTs). The effects of subthreshold-swing degradation, threshold-voltage roll-off, and drain-induced barrier lowering (DIBL) on the static current–voltage characteristics of staggered TFTs are extracted from an analytical potential solution of the 2-D problem of the staggered geometry. This solution is derived by using the Schwarz–Christoffel transformation that leads to a complex mapping function linking the staggered geometry to an equivalent in another coordinate system for which an analytical potential solution exists. The commercial TCAD is used to verify the compact models. Finally, the closed-form and physics-based equations are incorporated into an existing compact current model and verified by measurements on staggered organic TFTs with channel lengths as small as 0.4 µm fabricated on flexible plastic substrates by stencil lithography.

Fig:(a) Schematic cross section and (b) simplified geometry 

of the staggered organic TFTs for the TCAD simulations.

Acknowledgement: This work was supported in part by the German Federal Ministry of Education and Research under Grant 13FH015IX6 Strukturnahe Modellierung organischer flexibler KurzkanalTFTs (Structure-Oriented Modeling of Organic FLEXible short-channel TFTs) (SOMOFLEX), in part by the EU H2020 Marie Sklodowska-Curie actions (MSCA) Research and Innovation Staff Exchange (RISE) Project Design Oriented ModellINg for flexible electrOnics (DOMINO) under Grant 645760, and in part by the German Research Foundation (DFG) under Grant KL 1042/9-2 (SPP FFlexCom). 

[paper] Single Gate Extended Source Tunnel FET

Jagritee Talukdar^a, Gopal Rawat^b, Bijit Choudhuri^a, Kunal Singh^c, Kavicharan Mummaneni^a

Device Physics Based Analytical Modeling for Electrical Characteristics of Single Gate Extended Source Tunnel FET (SG-ESTFET)

Superlattices and Microstructures (2020): 106725

DOI: 10.1016/j.spmi.2020.106725

^aDECE, NIT Silchar, Assam, India
^bDECE, NIT Hamirpur, Himachal Pradesh, India
^cDECE, NIT Jamshedpur, Jharkhand, India

Abstract: In this paper, a 2D analytical model for Single Gate Extended Source Tunnel FET has been developed which is based on the solution of Poisson’s equation simplified using parabolic approximation method. Different electrical characteristics of device physics such as surface potential, drain current, lateral, and vertical electric field of SG-ESTFET are studied incorporating various parameters like mole fraction of SiGe layer, gate dielectric constants, etc. Furthermore, in modeling and simulation, the depletion region of the drain side is included considering the effect of the fringing field. The comercial TCAD device simulator has been used to verify the accuracy and validity of the proposed analytical model for various electrical parameters such as gate to source voltage, mole fraction, and gate dielectric constants. The validity of the proposed model is confirmed by observing a decent agreement between modeling and simulation. The proposed compact model delivers quick and accurate values of various performance parameters.

Fig: 2D schematic device structure of SG-ESTFET

[paper] Scaled GaN-HEMT Large-Signal Model Based on EM Simulation

Scaled GaN-HEMT Large-Signal Model Based on EM Simulation

Wooseok Lee¹, Hyunuk Kang¹, Seokgyu Choi², Sangmin Lee², Hosang Kwon³, Keum cheol Hwang¹, Kang-Yoon Lee¹ and Youngoo Yang¹

Electronics 2020, 9(4), 632

DOI: 10.3390/electronics9040632

¹Department of Electrical and Computer Engineering, Sungkyunkwan University, Suwon 16419, Korea
²Wavice Inc., Hwaseong-si 18449, Korea
³Agency for Defense Development, Daejeon 34186, Korea

Abstract This paper presents a scaled GaN-HEMT large-signal model based on EM simulation. A large-signal model of the 10-finger GaN-HEMT consists of a large-signal model of the two-finger GaN-HEMT and an equivalent circuit of the interconnection circuit. The equivalent circuit of the interconnection circuit was extracted according to the EM simulation results. The large-signal model for the two-finger device is based on the conventional Angelov channel current model. The large-signal model for the 10-finger device was verified through load-pull measurement. The 10-finger GaN-HEMT produced an output power of about 20 W for both simulation and load-pull measurements. 

Fig: Two-finger GaN-HEMT: a) layout; b) equivalent SPICE subcircuit

Acknowledgement: The research reported in this work has been supported by ADD (Agency of Defense Development) of Korea under an R&D program (UC170025FD).

[webinar] GaN HEMT Devices Characterization Using ASM-HEMT Model

ASM-HEMTモデルを使ったGaN HEMTデバイスの特性評価とモデリング

お知らせ: キーサイト・テクノロジーのウェブセミナー「ASM-HEMTモデルを使ったGaN HEMTデバイスの特性評価とモデリング 」

ライブウェブセミナーの日付: 2020年10月14日

ライブウェブセミナーの時刻: 10:45 JST

[paper] Compact Modeling of GaN HEMTs

Y. Chen et al., "Compact Modeling of THZ Photomixer Made from GaN HEMT," 2020 IEEE International Conference on Advances in Electrical Engineering and Computer Applications (AEECA), Dalian, China, 2020, pp. 484-489, doi: 10.1109/AEECA49918.2020.9213681.

Y. Chen et al., "A Surface Potential Based Compact Model for GaN HEMT I-V and CV Simulation," 2020 IEEE International Conference on Advances in Electrical Engineering and Computer Applications (AEECA), Dalian, China, 2020, pp. 490-495, doi: 10.1109/AEECA49918.2020.9213674.

A. Zhang et al., "Compact Modeling of Capacitance Components for GaN HEMTs," 2020 IEEE International Conference on Advances in Electrical Engineering and Computer Applications (AEECA), Dalian, China, 2020, pp. 505-511, doi: 10.1109/AEECA49918.2020.9213571.

FIG: Simplified GaN HEMT Structure

[paper] Parameter Extraction in JFETs

Nikolaos Makris¹, Matthias Bucher¹, Member, IEEE, Loukas Chevas¹, Farzan Jazaeri²

and Jean-Michel Sallese²

Free Carrier Mobility, Series Resistance, and Threshold Voltage Extraction
in Junction FETs

in IEEE Transactions on Electron Devices, 

Special Section on ESSDERC/ESSCIRC 2020

DOI: 10.1109/TED.2020.3025841.

¹School of Electrical and Computer Engineering, TU Crete (GR)

²Ecole Polytechnique Fédérale de Lausanne, EPFL (CH)

Abstract: In this brief, extraction methods are proposed for determining the essential parameters of double gate junction field-effect transistors (FETs). First, a novel method for determining free carrier effective mobility, similar to a recently proposed method for MOSFETs, is developed. The same method is then extended to cover also the case when series resistance is present, while series resistance itself may be determined from the measurement from two FETs with different channel lengths. The key technological and design parameter is the threshold voltage, which may be unambiguously determined from the transconductance-to-current ratio with a constant-current method. The new methods are shown to be effective over a wide range of technical parameters, using technology computer-aided design simulations.

Fig: Extraction of carrier mobility for DG JFETs in linear region at 300K 

a) corresponding output conductance gds and constituents ∂gds/∂Vds and 2Qsc,d/b, and 

b) extracted mobility for long- and moderate-length devices close agreement with the constant, nonfield-dependent mobility (μ = 826 cm2/Vs) used in the TCAD simulations.

Aknowlegement: This work was supported in part by the INNOVATION-EL-Crete Project under Grant MIS 5002772. 

[paper] Compact Modeling in MFIS Negative-Capacitance FETs

N. Pandey and Y. S. Chauhan

Analytical Modeling of Short-Channel Effects in MFIS Negative-Capacitance FET

Including Quantum Confinement Effects

in IEEE TED (Early Access), DOI: 10.1109/TED.2020.3022002.

Abstract: An analytical 2-D model of double-gate metal-ferroelectric-insulator-semiconductor-negative-capacitance FET (MFIS-NCFET), using Green's function approach, in the subthreshold region, is presented in this article. The explicit solution of coupled 2-D Landau-Devonshire and Poisson equations is analytically derived. Subsequently, an analytical and explicit model of subthreshold slope is developed from potential functions. The developed model includes quantum-mechanical effects, which considers not only geometrical confinements but also electrical confinements. The analytical solution of a 2-D nonhomogeneous Poisson equation coupled with the 1-D Schrödinger equation is used to obtain the potential function in the channel. The impact of the ferroelectric thickness (tfe) on quantum confinement is also studied. We find that larger tfe reduces the quantum confinement effect. Therefore, as tfe increases, threshold voltage roll-off with the variation in Si-body thickness decreases.

Fig: Schematic of DG MFIS-NCFET.

Aknowegement: This work was supported in part by the Swarna Jayanti Fellowship under Grant DST/SJF/ETA-02/2017-18 and in part by the FIST Scheme of the Department of Science and Tech- nology under Grant SR/FST/ETII-072/2016. 

Si2 VAMPyRE: compact model parser and checker

Si2 #Compact #Model #Coalition Offers VAMPyRE, the software is a standalone compact model parser and checker written in Python, to Members and Developers https://t.co/vPQWlcQ99l pic.twitter.com/gbUq5nBFOA

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[paper] Memristors in SPICE

Modeling networks of probabilistic memristors in SPICE

Vincent J. Dowling¹, Valeriy A. Slipko², Yuriy V. Pershin¹

arXiv:2009.05189v1 [cs.ET] 11 Sep 2020

DOI: 10.13164/re.2020.0001

¹Department of Physics and Astronomy, University of South Carolina, Columbia, SC 29208 USA
²Institute of Physics, Opole University, Opole 45-052, Poland

Abstract. Efficient simulation of probabilistic memristors and their networks requires novel modeling approaches. One major departure from the conventional memristor modeling is based on a master equation for the occupation probabilities of network states. In the present article, we show how to implement such master equations in SPICE. In the case studies, we simulate the dynamics of ac-driven probabilistic binary and multi-state memristors, and dc-driven networks of probabilistic binary and multi-state memristors. Our SPICE results are in perfect agreement with known analytical solutions. Examples of LTspice codes are included.

Fig: Ac-driven probabilistic binary memristor: (a) simulated circuit, (b) schematics of SPICE model, and (c) example of current-voltage curves found with SPICE simulations. The listing of SPICE model is given in Apendix.

Appendix: SPICE code examples

B1 0 p0 I=-gm(tau01,V01,V(Va))*V(p0)*u(V(Va))+gm(tau10,V10,-V(Va))*V(p1)*u(-V(Va))

B2 0 p1 I=gm(tau01,V01,V(Va))*V(p0)**u(V(Va))-gm(tau10,V10,-V(Va))*V(p1)**u(-V(Va))

C1 p0 0 1 IC=1

C2 p1 0 1 IC=.0

R2 Va 0 1k

R1 Va 0 10k

R3 VI 0 1k

B3 0 VI I=I(R1)*V(p0)+I(R2)*V(p1)

V1 Va 0 SINE(0 1 200 0 0 0 0)

.FUNC gm(x,y,z)1/(x*exp(-z/y))

.param tau01=3E5 V01=.05

.param tau10=3E5 V10=.05

.tran 0 .1 0.05 10E-7

.backanno

.end

[paper] Co-designing electronics with microfluidics

Remco van Erp, Reza Soleimanzadeh, Luca Nela, Georgios Kampitsis & Elison Matioli; Co-designing electronics with microfluidics for more sustainable cooling. Nature 585, 211–216 (2020). DOI: 10.1038/s41586-020-2666-1 https://t.co/WQ3ddWLuqp #paper pic.twitter.com/gqt3iVegwp

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2020 IEEE #IEDM To Highlight Innovative Devices for a #Better #Future

2020 IEEE #IEDM To Highlight Innovative Devices for a #Better #future https://t.co/8m1toPqhfI #paper pic.twitter.com/3FlTSlo3Id

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OFETs Compact Modeling

Advances in Compact Modeling of Organic Field-Effect Transistors

Sungyeop Jung¹, Member, IEEE, Yvan Bonnassieux², Gilles Horowitz², Sungjune Jung¹, Member, IEEE, Benjamin Iñiguez³, Fellow, IEEE, and Chang-Hyun Kim⁴, Senior Member, IEEE

IEEE J-EDS (Early Access)

DOI: 10.1109/JEDS.2020.3020312

¹Future IT Innovation Laboratory and Department of Creative IT Engineering, Pohang University of Science and Technology, Pohang 37673, South Korea.
²LPICM, Ecole Polytechinque, CNRS, 91128 Palaiseau, France.

³DEEEA, Universitat Rovira i Virgili, Tarragona 43007, Spain.

⁴Department of Electronic Engineering, Gachon University, Seongnam 13120, South Korea

Abstract: In this review, recent advances in compact modeling of organic field-effect transistors (OFETs) are presented. Despite the inherent strength for printed flexible electronics and the extremely aggressive research conducted over more than three decades, the OFET technology still seems to remain at a relatively low technological readiness level. Among various possible reasons for that, the lack of a standard compact model, which effectively bridges the device- and system-level development, is clearly one of the most critical issues. This paper broadly discusses the essential requirements, up-to-date progresses, and imminent challenges for the OFET compact device modeling toward a universal, physically valid, and applicable description of this fast-developing technology.

Figure (a) Cross-sectional illustration and (b) circuit diagram with multi-component overlap capacitances of the printed 3-D organic complementary inverter, and (c) measured and simulated transient output voltage of an 11-stage ring oscillator.

#Special Issue: The 11th International Symposium on Electric and Magnetic Fields (#EMF 2018) https://t.co/pVDWOoLXC4 #paper https://t.co/HqmYxemttD

#Special Issue: The 11th International Symposium on Electric and Magnetic Fields (#EMF 2018) https://t.co/pVDWOoLXC4 #paper pic.twitter.com/HqmYxemttD

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IEEE International Electron Devices Meeting to be Held Virtually https://t.co/LGJVdu1TyN https://t.co/vVgVsLrX4I #paper https://t.co/XN5oesBAQE

IEEE International Electron Devices Meeting to be Held Virtually https://t.co/LGJVdu1TyNhttps://t.co/vVgVsLrX4I#paper pic.twitter.com/XN5oesBAQE

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#Intel conceding the battle to #ARM and #AMD as 7nm processors delayed even further https://t.co/FHOPn7AA0O #paper

#Intel conceding the battle to #ARM and #AMD as 7nm processors delayed even further https://t.co/FHOPn7AA0O#paper

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[paper] Compact Model of All-Optical-Switching Magnetic Elements

J. Pelloux-Prayer¹ and F. Moradi¹

Compact Model of All-Optical-Switching Magnetic Elements

IEEE TED, vol. 67, no. 7, pp. 2960-2965, July 2020

DOI: 10.1109/TED.2020.2991330.

¹Department of Engineering, Aarhus University, 8200 Aarhus, Denmark

Abstract: We present, for the first time, a Verilog-A compact model for an all-optically switchable magnetic tunnel junction (MTJ) using results of all-optical-switching (AOS) simulations. Our model is compatible with electronics and photonics design automation tools, and was tested using Cadence Specter and Virtuoso. This compact model can be used to design circuits and systems combining MTJs, photonic circuits, and electronic circuits giving the possibility to researchers working within this field to develop novel circuits and systems.

Fig: Equivalent circuit of the AOS model with LLGS module and LUT module.

Aknowledgement: This work was supported by the European Union’s Horizon 2020 Research and Innovation Programme under Grant 713481.

[FOSSi] #Free #chips courtesy of Google, SkyWater, eFabless https://t.co/sZOyCTuty4 #paper https://t.co/xqwS9nl3Ir

[FOSSi] #Free #chips courtesy of Google, SkyWater, eFabless https://t.co/sZOyCTuty4#paper pic.twitter.com/xqwS9nl3Ir

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