[paper] Optomechanical Sensor in Verilog-A

Houssein Elmi Dawale, Loïc Sibeud, Sébastien Regord, Guillaume Jourdan, Member, IEEE, Sébastien Hentz, Member, IEEE, and Franck Badets, Senior Member, IEEE

Compact Modeling and Behavioral Simulation of an Optomechanical Sensor in Verilog-A

IEEE Transactions on Electron Devices, vol. 67, no. 11, pp. 4677-4681, Nov. 2020

DOI: 10.1109/TED.2020.3024477

Abstract: Previous work has shown that optomechanical resonators are particularly well suited to the design of ultrasensitive mass sensors. They present an extremely low noise level, very high optical quality factor (Q>105), excellent integration density and can resonate both in a gaseous and liquid environment. In order to reduce the long measurement time due to their small particle capture area, several such resonators must be integrated onto the same chip. However, bulky laboratory equipment currently used to read a single optomechanical resonator cannot be practically scaled up to a large array of transducers. It is then required to design and eventually integrate a read-out interface that can process tens to thousands of resonators. To ease the design of such a circuit, this article presents a compact analytical model of an electrostatically actuated optomechanical resonator implemented in Verilog-A. The proposed model includes both the optical and mechanical behaviors, as well as optomechanical coupling and thermo-optical effect. It was simulated in commercial simulator and is consistent with the measured results. 

FIG: a) General view of the optomechanical device with electrostatic actuation. 

b) Functional diagram of the device in Verilog-A.

[paper] Compact Models for IGBTs

Advanced physics-based compact models for new IGBT technologies

Arnab Biswas, Maria Cotorogea

Infineon Technologies AG, Germany

Abstract The TRENCHSTOP™ IGBT7 technology is based on the latest micro-pattern trench technology. It provides strongly reduced losses offering a high level of controllability [1]. This technology brings forward new challenges in compact modelling. Current IGBT compact models at Infineon are physics-based subcircuit representations in SPICE syntax. They were developed to run in the circuit simulator SIMetrix, and are manually calibrated. The aim of this work is to present advanced models for the micro-pattern trench IGBT implemented in Verilog-A language, addressing the challenges of compact models in terms of calibration accuracy, simulation run time, model robustness and portability to multiple simulators.

Fig. 3: IGBT technology overview showing schematically

the static excess-carrier density distribution in the plasma region.

[paper] Compact Model of All-Optical-Switching Magnetic Elements

J. Pelloux-Prayer¹ and F. Moradi¹

Compact Model of All-Optical-Switching Magnetic Elements

IEEE TED, vol. 67, no. 7, pp. 2960-2965, July 2020

DOI: 10.1109/TED.2020.2991330.

¹Department of Engineering, Aarhus University, 8200 Aarhus, Denmark

Abstract: We present, for the first time, a Verilog-A compact model for an all-optically switchable magnetic tunnel junction (MTJ) using results of all-optical-switching (AOS) simulations. Our model is compatible with electronics and photonics design automation tools, and was tested using Cadence Specter and Virtuoso. This compact model can be used to design circuits and systems combining MTJs, photonic circuits, and electronic circuits giving the possibility to researchers working within this field to develop novel circuits and systems.

Fig: Equivalent circuit of the AOS model with LLGS module and LUT module.

Aknowledgement: This work was supported by the European Union’s Horizon 2020 Research and Innovation Programme under Grant 713481.

[RG] research paper reached 500 citations

FOSS EKV2.6 Verilog-A Compact MOSFET Model

Wladek Grabinski¹, Marcelo Pavanello², Michelly de Souza², Daniel Tomaszewski³, Jola Malesinska³, Grzegorz Głuszko³, Matthias Bucher⁴, Nikolaos Makris⁴, Aristeidis Nikolaou⁴, Ahmed Abo-Elhadid⁵, Marek Mierzwinski⁶, Laurent Lemaitre⁷, Mike Brinson⁸, Christophe Lallement⁹, Jean-Michel Sallese¹⁰, Sadayuki Yoshitomi¹¹, Paul Malisse¹², Henri Oguey¹³, Stefan Cserveny¹³, Christian Enz¹⁰, François Krummenacher¹⁰ and Eric Vittoz¹⁰ 

in 49th European Solid-State Device Research Conference 

(ESSDERC; pp. 190-193)

DOI: 10.1109/essderc.2019.8901822 

FOSS EKV2.6 Verilog-A at GitHub https://github.com/ekv26/model

¹ MOS-AK Association (EU), 
² Centro Universitario FEI, Sao Bernardo do Campo (BR), 
³ Institute of Electron Technology, Warsaw (PL), 
⁴ Technical University of Crete, Chania (GR), 
⁵ Mentor Graphics (USA), 
⁶ Keysight Technologies (USA), 
⁷ Lemaitre EDA Consulting, 
⁸ London Metropolitan University (UK), 
⁹ ICube, Strasbourg University (F), 
¹⁰ EPFL Lausanne, 
¹¹ Toshiba (J), 
¹² Europractice/IMEC (B), 
¹³ CSEM S.A., Neuchatel (CH)

[paper] BSIM-HV: High-Voltage MOSFET Model

H. Agarwal , Member, IEEE, C. Gupta , Graduate Student Member, IEEE, R. Goel , Graduate Student Member, IEEE, P. Kushwaha , Member, IEEE, Y.-K. Lin , Graduate Student Member, IEEE, M.-Y. Kao , Graduate Student Member, IEEE, J.-P. Duarte , Graduate Student Member, IEEE, H.-L. Chang , Member, IEEE, Y. S. Chauhan , Senior Member, IEEE, S. Salahuddin, Fellow, IEEE, and C. Hu, Life Fellow, IEEE

BSIM-HV: High-Voltage MOSFET Model Including Quasi-Saturation and Self-Heating Effect

IEEE TED, vol. 66, no. 10, pp. 4258-4263, Oct. 2019

doi: 10.1109/TED.2019.2933611

Abstract - A BSIM-based compact model for a high-voltage MOSFET is presented. The model uses the BSIM-BULK (formerly BSIM6) model at its core, which has been extended to include the overlap capacitance due to the drift region as well as quasi-saturation effect. The model is symmetric and continuous, is validated with the TCAD simulations and experimental 35- and 90V LDMOS and 40V VDMOS transistors, and shows excellent agreement.

FIG: Schematic of the LDMOS. Lightly doped n-region constitutes the drain. Majority of the applied drain voltage drops across this region, which protects the intrinsic transistor region from breakdown.

Manuscript received March 3, 2019; revised May 23, 2019 and July 24, 2019; accepted July 31, 2019. Date of publication August 26, 2019; date of current version September 20, 2019. This work was supported in part by the members of the Berkeley Center for Negative Capacitance Technology and the members of the Berkeley Device Modeling Center. The review of this article was arranged by Editor B. Iñiguez.

PhD Positions at Institute for Microelectronics/TU Wien

PhD Positions
on Characterization, Modeling and Circuit Simulation in Microelectronics
Institute for Microelectronics/TU Wien

The Institute for Microelectronics is a world leading research institute focused on the reliability of circuit components (especially transistors). In addition to conventional Si transistors, the behavior of SiC devices designed for high-power applications is also at the center of interest. The broad field of research conducted at the Institute of Microelectronics ranges from characterization, physical modeling and ab-initio simulations to compact modeling and circuit simulation. For the characterization of transistors, the Institute for Microelectronics has a modern laboratory equipped with commercial and custom-built measurement instruments. To explain the experimental data, elaborate physical models are developed and constantly improved. The models are directly incorporated into state-of-the-art device simulators, i.e. MinimosNT and Comphy. To perform computationally expensive simulations a modern computer cluster is while for circuit simulations Cadence and Synopsis spice simulators are available.

The institute is currently looking for highly talented and motivated young researchers to join the team in one of the following areas:

• Physical modeling of silicon-carbide transistors
• Single-defect characterization of low-noise silicon transistors
• Development of custom-made measurement instruments
• Circuit simulations using advanced implementation of reliability models in Verilog-A for SPICE

For the positions knowledge in one or more of the following areas is advantageous to complement our team:

• C/C++ and Python
• Semiconductor device physics
• Circuit simulation
• Implementation of new compact/physical models
• Handling of device/circuit simulators
• Design of discrete analog circuits and hardware/software solutions
• Wafer probers and instruments for microelectronics
• Keithley instruments and scripting language LUA
• Measurement techniques in microelectronics (MSM, C(V), DLTS, charge pumping etc.)

As a teaching institution, knowledge transfer and close cooperation with students are very importance. The applicants should like to work together with students and supervise Master’s and Bachelor theses.

Starting Date: As soon as possible

Salary: Three-year positions (40hours/week) are in accordance with the salary regulations of the Austrian Science Fund. The gross annual salary is approximately EUR 40,300

Application Material: Please provide a detailed CV, your collective certificates, your Master’s thesis (weblink or PDF), and a single-page motivation letter (discussing relevant previous experience related to the desired skills and experiences) and summarize your motives for joining us.

Application: Please submit your application to jobs@iue.tuwien.ac.at.

Application Deadline: The positions will remain open until filled.

[open source paper] Open-source circuit simulation tools for RF compact semiconductor device modelling

Open-source circuit simulation tools for RF compact semiconductor device modelling

Wladek Grabinski (editor), Mike Brinson, Paolo Nenzi, Francesco Lannutti, Nikolaos Makris, Angelos Antonopoulos and Matthias Bucher

September 2014

DOI: 10.1002/jnm.1973

SUMMARY: MOS-AK is a European, independent compact modelling forum created by a group of engineers, researchers and compact modelling enthusiasts to promote advanced compact modelling techniques and model standardization using high level behavioral modelling languages such as VHDL-AMS and Verilog-A. This invited paper summarizes recent MOS-AK open source compact model standardization activities and presents advanced topics in MOSEFT modelling, focusing in particular on analogue/RF applications. The paper discusses links between compact models and design methodologies, finally introducing elements of compact model standardization. The open source CAD tools: Qucs, QucsStudio and ngspice all support Verilog-A as a hardware description language for compact model standardization. Latter sections of this paper describe a Verilog-A implementation of the EKV3 MOS transistor model. Additionally, the simulated  RF model performance is evaluated and compared with experimental results for 90nm CMOS technology. 

KEYWORDS: CAD; GNU; Qucs; QucsStudio; ngspice; compact modeling; EKV3; RF; MOSFET; Verilog-A

IEEE TED SI on Compact Modeling for Circuit Design

Special Issue on Compact Modeling for Circuit Design

Benjamin Iñiguez, Wladek Grabinski, Slobodan Mijalković, Kejun Xia, Andries J. Scholten, Yogesh Singh Chauhan, Ananda S. Roy, Sadayuki Yoshitomi, Kaikai Xu

in IEEE Transactions on Electron Devices, vol. 66, no. 1, Jan. 2019.

doi: 10.1109/TED.2018.2884284

Abstract: This Special Issue is dedicated to recent research in the field of compact modeling for circuit design. The topics included all device structures, provided it was demonstrated that the presented compact modeling solutions were implementable in circuit design tools. The last Special Issue addressing compact modeling of all types of semiconductor devices was published in 2006. Since then, new device structures, and with different materials, have emerged, and significant and successful research in compact advance device modeling has been done, as well in the application of compact models to circuit design. Therefore, a new Special Issue was needed that could include high-quality papers in these topics.

This Special Issue is dedicated to recent research in the field of compact modeling for circuit design. The topics included all device structures, provided it was demonstrated that the presented compact modeling solutions were implementable in circuit design tools. The last Special Issue addressing compact modeling of all types of semiconductor devices was published in 2006. Since then, new device structures, and with different materials, have emerged, and significant and successful research in compact advance device modeling has been done, as well in the application of compact models to circuit design. Therefore, a new Special Issue was needed that could include high-quality papers in these topics.

A total of 60 regular papers were submitted to this Special Issue, of which 21 were accepted. Besides, the Special Issue includes four invited papers. All papers, including the invited ones, were subjected to thorough peer review. A high number of reviewers have participated in this process. This has resulted in a Special Issue containing very high-quality papers.

The published papers target compact modeling aspects for a wide number of devices: several MOSFET structures, tunnel FETs, HEMTs, nanowire FETs, TMD FETs, TFTs, OLEDs, solar cells, photodiodes, and so on.Besides, different operation regimes and analyses are addressed: dc, RF, HV, ballistic regime, variability, reliability, aging, and so on.

The four invited papers also target different topics. The paper by C. C. McAndrew is focused on the successes and challenges of MOS compact models. S. Dongaonkar et al. address the opportunities and challenges of circuit design methodologies ranging from process corners to statistical circuit design. P. Zampardi et al. discuss the industrial view of III–V device compact modeling for circuit design. Finally, Madec et al. target a quite different and challenging environment for the modeling of biosensors, biosystems, and lab-on-chips.

I would like to thank the work done by the rest of the Editors of this Special Issue and also by all the reviewers who participated in this process. And of course, I want to thank all the authors for their interest in submitting papers to this Special Issue. Thanks to authors, reviewers, and editors, this high-quality Special Issue has been possible.

[paper] Well-Posed Device Models for Electrical Circuit Simulation

Well-Posed Device Models for Electrical CircuitSimulation
A Guide to Creating Robust Device Models
A. Gokcen Mahmutoglu, Tianshi Wang, Archit Gupta and Jaijeet Roychowdhury
March 25, 2017

Synopsis: This document provides guidelines for creating computational device models that work well in simulation. We build our discussion around the mathematical notion of “well-posedness”. We show that the requirements for a model to be well-posed stem from the internal working mechanisms of simulators. Therefore, our main aim is to provide insight into the numerical procedures used by simulators in order to help model developers avoid ill-posedness issues. We start our discussion with an example that shows how an ill-posed Verilog-A model can produce different simulation results in different simulators. We then provide a step-by-step simulation case study. In this case study, we illustrate the role of device models in simulations by examining the steps a simulator goes through, from taking a netlist as input to producing a simulation result as output. Finally, we distill our discussion in a functional definition of a well-posed model. As an extension to our theoretical discussion, we also provide practical guidelines that should be followed by Verilog-A models in order to avoid ill-posedness issues [read more...]

This document is published as a part of the Nano-Engineered Electronic Device Simulation (NEEDS) initiative. NEEDS is an NSF-funded initiative whose charter includes the development of tools and techniques for the production of high-quality device models¹:
NEEDS has a vision for a new era of electronics that couples the power of billion-transistor CMOS technology with the new capabilities of emerging nano-devices and a charter to create high-quality models and a complete development environment that enables a community of compact model developers.

NEEDS Team: Purdue, MIT, UC Berkeley, and Stanford.”

¹For more information about NEEDS please visit https://nanohub.org/groups/needs/.

A Guide to Creating Robust Device Models

Well-Posed Device Models for Electrical Circuit Simulation
A Guide to Creating Robust Device Models
A. Gokcen Mahmutoglu, Tianshi Wang, Archit Gupta and Jaijeet Roychowdhury
March 25, 2017

Synopsis: This document provides guidelines for creating computational device models that work well in simulation. We build our discussion around the mathematical notion of “well-posedness”. We show that the requirements for a model to be well-posed stem from the internal working mechanisms of simulators. Therefore, our main aim is to provide insight into the numerical procedures used by simulators in order to help model developers avoid ill-posedness issues. We start our discussion with an example that shows how an ill-posed Verilog-A model can produce different simulation results in different simulators. We then provide a step-by-step simulation case study. In this case study, we illustrate the role of device models in simulations by examining the steps a simulator goes through, from taking a netlist as input to producing a simulation result as output. Finally, we distill our discussion in a functional definition of a well-posed model. As an extension to our theoretical discussion, we also provide practical guidelines that should be followed by Verilog-A models in order to avoid ill-posedness issues.

This document is published as a part of the Nano-Engineered Electronic Device Simulation (NEEDS) initiative. NEEDS is an NSF-funded initiative whose charter includes the development of tools and techniques for the production of high-quality device models¹:

“NEEDS has a vision for a new era of electronics that couples the power of billion-transistor CMOS technology with the new capabilities of emerging nano-devices and a charter to create high-quality models and a complete development environment that enables a community of compact model developers.

NEEDS Team: Purdue, MIT, UC Berkeley, and Stanford.”

¹For more information about NEEDS please visit https://nanohub.org/groups/needs/
https://nanohub.org/resources/26200/download/well-posed_device_models-29453e4.pdf

100 reads: Compact Device Modeling using Verilog-AMS and ADMS

Article reached 100 reads: Compact device modeling using Verilog-AMS and ADMS
Lemaitre L · Grabiński W · McAndrew C
Abstract: This paper shows how high level language as Verily-AMS can serve as support for compact modeling development of new devices. First section gives a full Verily-AMS code of a simplified bipolar transistor. Each part of the code is carefully examined and explained. Second section compared different implementations if the simplified bipolar transistor in different spice simulators. ADMS, an open-source tool developed at Motorola, performs the implementations from Verily-AMS to simulators. Third sections concludes the paper by describing by implementation of the EKV model into ADS using the compact model interface provided by Agilent.
View publication
12 citations 107 reads

[Call for Participation] FOSDEM 2016 Electronic Design Automation Devroom

 Call for Participation 

FOSDEM 2016 Electronic Design Automation Devroom 

This is the call for participation in the FOSDEM 2016 devroom on Free/Open Source Software (FOSS) Electronic Design Automation (EDA) tools, to be held on Saturday 30 January 2016 in Brussels, Belgium. We are looking for contributions under the form of talks covering the following main topics:

• Printed Circuit Board (PCB) design tools (e.g. KiCad and gEDA)
• Analogue and digital simulators (e.g. ngspice, Qucs, Gnucap, Xyce, GHDL, Icarus and Verilator)
• Any other EDA tools such as high-level tools for digital hardware design (e.g. Migen)
• Inter-project opportunities for collaboration

We hope to provide an opportunity for attendees to bring themselves up to date on the latest FOSS EDA developments, share knowledge and identify opportunities to collaborate on development tasks. Have a look at last year's event for a taste of what the EDA devroom is about.

The submission process
Please submit your proposals at https://penta.fosdem.org/submission/FOSDEM16 

before 4 December 2015.

If you already have a Pentabarf account (for example as a result of having submitted a proposal in the past), make sure you use it to log in and submit your proposal. Do not create a new account if you already have one. Please provide a bit of information about yourself under Person -> Description -> Abstract. When you submit your proposal (creating an "Event" in Pentabarf), make sure you choose the "EDA devroom" in the track drop-down menu. Otherwise your proposal might go unnoticed. Fill in at least a title and abstract for the proposed talk and a suggested duration. Bear in mind that a lot of the value in these meetings comes from the discussions, so please be reasonable regarding the duration of the talk.

Important dates

• 4 December 2015: deadline for submission of proposals
• 18 December 2015: announcement of final schedule
• 30 January 2016: devroom day

[Read More]

IEDM: Modeling and Simulation – Compact Modeling

 IEEE International Electron Devices Meeting (IEDM) is the world’s preeminent forum for reporting technological breakthroughs in the areas of semiconductor and electronic device technology, design, manufacturing, physics, and modeling. IEDM is the flagship conference for nanometer-scale CMOS transistor technology, advanced memory, displays, sensors, MEMS devices, novel quantum and nano-scale devices and phenomenology, optoelectronics, devices for power and energy harvesting, high-speed devices, as well as process technology and device modeling and simulation. This year IEDM technical program also includes a series of the compact modeling papers:

[9.6] GaNFET Compact Model for Linking Device Physics, High Voltage Circuit Design and Technology Optimization, U. Radhakrishna, S. Lim, P. Choi, T. Palacios, and D.A Antoniadis, Massachusetts Institute of Technology
[28.1] Transport Mechanism in sub 100C Processed High Mobility Polycrystalline ZnO Transparent Thin Film Transistors, P.B. Pillai, and M.M. De Souza, University of Sheffield
[28.2] Physical-based Analytical Model of flexible a-IGZO TFTs Accounting for Both Charge Injection and Transport, M. Ghittorelli, F. Torricelli, J.L. Van Der Steen*, C. Garripoli**, A. Tripathi*, G. Gelinck*, E. Cantatore**, Z. Kovacs-Vajna, University of Brescia, *Holst Centre, TNO, **Eindhoven University of Technology
[28.3] Predictive Compact Modeling of Random Variations in FinFET Technology for 16/14nm Node and Beyond, X. Jiang, X. Wang*, R. Wang, B. Cheng**, A. Asenov*, and R. Huang, Peking University, *University of Glasgow, **Gold Standard Simulations (GSS) Ltd.
[28.4] A New Surface Potential Based Physical Compact Model for GFET in RF Applications, L. Wang, S. Peng, Z. Zong, L. Li, W. Wang, G. Xu, N. Lu, Z. Ji, and M. Liu, Chinese Academy of Sciences
[28.5] Physics-based Compact Modeling Framework for State-of-the-Art and Emerging STT-MRAM Technology, N. Xu, J. Wang, Y. Lu, H.-H. Park, B. Fu, R. Chen, W. Choi, D. Apalkov, S. Lee*, S. Ahn*, Y. Kim*, Y. Nishizawa**, K.-H. Lee, Y. Park, Samsung Semiconductor Inc, *Samsung Electronics, **Samsung R&D Institute Japan
[28.6] Physics-based Compact Modeling of Charge Transport in Nanoscale Electronic Devices (Invited), S. Rakheja, and D. Antoniadis*, New York University, *Massachusetts Institute of Technology

The compact/SPICE modeling and its Verilog-A standardization will be also discussed at two following engineering events organized by MOS-AK Group and the CMC which are collocated with the IEDM in Washington DC in December, later this year.

[online MOS-AK and CMC registration]

• MOS-AK Workshop in Washington DC (Dec.9) 
• http://www.mos-ak.org/washington_dc_2015/
• CMC Meeting at Sheraton Suites Old Town Alexandria (Dec.10-11)
• https://www.si2.org/openeda.si2.org/4Q_2015_CMC_Meeting.php

MOS-AK article reached 400 reads

 MOS-AK article reached 400 reads

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   Open-Source Circuit Simulation Tools for RF Compact Semiconductor Device Modelling

  September 2014 · International Journal of Numerical Modelling Electronic Networks Devices an...

   Wladek Grabinski · Mike Brinson · Paolo Nenzi · Francesco Lannutti· Nikolaos Makris · Angelos Antonopoulos · Matthias Bucher 

  Abstract: MOS-Modelle und Parameterextraktion Arbeitskreis (MOS-AK) is a European, independent compact modelling forum created by a group of engineers, researchers and compact modelling engineers...

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  1 CITATION 401 READS

Best Practices for Compact Modeling in Verilog-A

Mcandrew, C.C.; Coram, G.J.; Gullapalli, K.K.; Jones, J.R.; Nagel, L.; Roy, A.S.; Roychowdhury, J.; Scholten, A.J.; Smit, G.D.J.; Wang, X.; Yoshitomi, S., "Best Practices for Compact Modeling in Verilog-A," Electron Devices Society, IEEE Journal of the , vol.PP, no.99, pp.1,1

doi: 10.1109/JEDS.2015.2455342

Abstract: Verilog-A is the de facto standard language that the semiconductor industry uses to define compact models. Unfortunately, it is easy to write models poorly in Verilog-A, and this can lead to unphysical model behavior, poor convergence, and difficulty in understanding and maintaining model codes. This paper details best practices for writing compact models in Verilog-A, to try to help raise the quality of compact modeling throughout the industry.

keywords: Capacitance, Computational modeling, Convergence, Hardware design languages, Integrated circuit modeling, Mathematical model, Numerical models

[read more...]

REFERENCES[1] S. Liu, K. C. Hsu, and P. Subramaniam, “ADMIT-ADVICE modeling interface tool,” Proc. IEEE Customs Integrated Circuits Conf., pp. 6.6.1- 6.6.4, 1988.
[2] M. Vlach, “Modeling and simulation with Saber,” Proc. 3rd Annual ASIC Seminar and Exhibit, pp. T11.1-T11.9, 1990.
[3] E. McReynolds, personal communication, circa 1995.
[4] E. Christen and K. Bakalar, “VHDL-AMS—A hardware description language for analog and mixed-signal applications,” IEEE Trans. Circuits and Systems II, vol. 46, no. 10, pp. 1263-1272, Oct. 1999.
[5] [Online]: http://www.accellera.org/downloads/standards/v-ams (accessed June, 2015).
[6] L. Lemaitre, G. Coram, C. McAndrew, and K. Kundert, “Extensions to Verilog-A to support compact device modeling,” Proc. IEEE Behavioral Modeling and Simulation Workshop, pp. 134-138, Oct. 2003.
[7] L. Zhou, B. P. Hu, B. Wan, and C.-J. R. Shi, “Rapid BSIM model implementation with VHDL-AMS/Verilog-AMS and MCAST compact
model compiler,” IEEE Int. SOC Conf., pp. 285-286, Sep. 2003.
[8] G. Coram and M. Ding, “Recent achievements in Verilog-A compact modeling,” MOS-AK Workshop, Dec. 2009.
[9] G. Coram, “How to (and how not to) write a compact model in Verilog- A,” Proc. IEEE Behavioral Modeling a Simulation Workshop, pp. 97-106, Oct. 2004.
[10] G. Coram and C. C. McAndrew, “Verilog-A for compact modeling: best practices for high-quality model authoring,” Workshop on Compact Modeling for RF, Sep. 2005.
[11] G. Coram, “Verilog-A: an introduction for compact modelers,” MOS-AK Workshop, Sep. 2006.
[12] M. Mierzwinski, P. O’Halloran, and B. Troyanovsky, “Developing and releasing compact models using Verilog-A,” MOS-AK Workshop, Dec. 2008.
[13] G. Depeyrot and F. Poullet, “Guidelines for Verilog-A compact model coding,” MOS-AK Workshop, Sep. 2009.
[14] M. Mierzwinski, P. O’Halloran, and B. Troyanovsky, “Practical considerations for developing, debugging, and releasing Verilog-A models,” MOS-AK Workshop, Dec. 2009.
[15] C. C. McAndrew and G. Coram, “General and junction primitives for Verilog-A compact models,” nanoHUB. doi:10.4231/D3G15TC2J, 2015.
[16] C. C. McAndrew, “R3,” nanoHUB. doi:10.4231/D3QB9V64G, 2014.
[17] L. W. Nagel, SPICE2: A Computer Program to Simulate Semiconductor Circuits, Memo. ERL-M520, Univ. California, Berkeley, May 1975.
[18] X. Li, W. Wu, G. Gildenblat, C. C. McAndrew, and A. J. Scholten, “Benchmark tests for MOSFET compact models,” in Compact Modeling: Principles, Techniques and Applications, G. Gildenblat (Ed), Springer, pp. 75-104, 2010
[19] Y. Tsividis and C. McAndrew, Operation and Modeling of the MOS Transistor, 3rd ed., New York: Oxford University Press, 2011.
[20] [Online]: http://physics.nist.gov/cuu/Constants/Citations/Search.html (accessed June, 2015)
[21] A. Parker, “Getting to the heart of the matter,” IEEE Microwave Magazine, vol. 16, no. 3, pp. 76-86, Apr. 2015. [22] H. K. Dirks, Kapazit¨atskoeffizienten nichtlinearer dissipativer Systeme, Habilitation Theses, RWTH Aachen University, 1998.
[23] A. C. T. Aarts, R. van der Hout, J. C. J. Paasschens, A. J. Scholten, M. B. Willemsen, and D. B. M. Klaassen, “New fundamental insights into capacitance modeling of laterally nonuniform MOS devices,” IEEE Trans. Electron Dev., vol. 53, no. 2, pp. 270-278, Feb. 2006.
[24] C. C. McAndrew, “Practical modeling for circuit simulation,” IEEE J. Solid-State Circuits, vol. 33, no. 3, pp. 439-448, Mar. 1998.
[25] C. C. McAndrew, “Useful numerical techniques for compact modeling,” Proc. IEEE ICMTS, pp. 121-126, Apr. 2002. [26] K. Kundert, “Hidden state in SpectreRF,” [Online]: http://http://www.designers-guide.org/analysis/hidden-state.pdf (accessed June, 2015)
[27] R. K. Johnson, The Elements of MATLAB R⃝ Style, Cambridge University Press, 2011.
[28] M. Driessen and D. B. M. Klaassen, personal communication, 2006.
[29] [Online]: https://nanohub.org/groups/needs (accessed June, 2015)
[30] L. Lemaitre, C. C. McAndrew, and S. Hamm, “ADMS-automated device model synthesizer,” Proc. IEEE CICC, pp. 27-30, May 2002.
[31] [Online]: http://sourceforge.net/projects/mot-adms/ (accessed June, 2015)

i-MOS version 201410 release

  New release of the interactive Modeling and On-line Simulation Platform (i-MOS), version 201410 has been released. In this release we have launched some new features:

• Developing an ‘Equalizer’ module in the ‘Model’ page for easy model parameter tuning
• Accommodating multiple parameters in this module for users’ most convenience
• Improving the ‘Custom data’ function for manual parameter extractions
• Updating the TFET model e-TIM (previous e-TuT) to support multiple materials
• Including an am-bipolar current module in the e-TIM

The new  release is ready here i-MOS.

[mos-ak] [on-line publications] Spring MOS-AK Workshop in London

  

Recent, Spring MOS-AK Workshop at the London Metropolitan University was organized to discuss SPICE/compact modeling and its standardization with following Qucs GPL circuit simulation tutorial. The workshop's presentations are available on-line at <http://www.mos-ak.org/london_2014/>.

   

Please also distribute further information about next MOS-AK related events among all who are interested in the SPICE/compact modeling and its Verilog-A standardization:

• 3rd International Training Course on Compact Modelling (TCCM) Lublin (PL) June 18, 2014
• http://compactmodelling.eu/tccm3_about.php
• MIXDES Special Compact Modeling Session, Lublin (PL) June 19-21, 2014
• http://www.mixdes.org/Mixdes3/tekst/view/special
• 12th MOS-AK ESSDERC/ESSCIRC Workshop, Venice (I) Sept. 26, 2014
• http://www.mos-ak.org/venice_2014/
• 7th International MOS-AK Workshop San Francisco (US) Dec. 2014
• http://www.mos-ak.org/

Already now, I am looking forward to meet you at one of our MOS-AK modeling events, soon.

-- with regards - wladek for the Extended MOS-AK/GSA Committee;

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Arbeitskreis Modellierung von Systemen und Parameterextraktion 

Modeling of Systems and Parameter Extraction Working Group

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Over two decades of Enabling Compact Modeling R&D Exchange

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http://www.mos-ak.org

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