[paper] Gate Tunneling Current in MFIS NCFETs

Kshitiz Tyagi, Amit Verma, and Aloke K. Dutta

Modeling of the Gate Tunneling Current in MFIS NCFETs

IEEE Transactions on Electron Devices, pp. 1–8, Sept.18, 2021.

DOI: 10.1109/TED.2021.3114386

  

Department of Electrical Engineering, Indian Institute of Technology Kanpur, Kanpur 208016, India

  

Abstract: In this article, we present a model for the gate tunneling current (GTC) in metal-ferroelectric-insulator-semiconductor (MFIS) negative capacitance FETs (NCFETs), which, to the best of our knowledge, is the first such report. The model is numerical in nature, and is developed using the Tsu–Esaki formulation, employing the Wentzel–Kramer–Brillouin (WKB) approximation, in order to estimate the transmission coefficients of the carriers through the barriers. The ferroelectric (FE) material considered is HfO2, and is modeled using the Landau phase transition theory. Simulation results reveal a remarkable nonmonotonic dependence of the GTC on the FE layer thickness, an effect that we explain through the Landau model. Furthermore, it is shown how this GTC can be reduced by orders of magnitude without changing the overall dielectric capacitance-a feature that may prove to be beneficial in low-power circuit designs. Additionally, it is seen that the GTC is a weak function of the remanent polarization and coercive field of the FE. All the model predictions are validated through a comparison with the results obtained from 2-D TCAD simulations. The novel results presented in this work should serve as a guide for detailed experimental studies on the gate current characteristics of MFIS NCFETs.

Fig: Direct (DT) and Fowler–Nordheim (FN) tunneling modes of electrons having various energies, from the Si conduction band to the gate region

Acknowledgment: The authors would like to acknowledge the help of Mr. Amol Gaidhane at Nanolab, IIT Kanpur, in setting up the TCAD simulation workbench

[paper] Parameter Extraction in JFETs

Nikolaos Makris¹, Matthias Bucher¹, Member, IEEE, Loukas Chevas¹, Farzan Jazaeri²

and Jean-Michel Sallese²

Free Carrier Mobility, Series Resistance, and Threshold Voltage Extraction
in Junction FETs

in IEEE Transactions on Electron Devices, 

Special Section on ESSDERC/ESSCIRC 2020

DOI: 10.1109/TED.2020.3025841.

¹School of Electrical and Computer Engineering, TU Crete (GR)

²Ecole Polytechnique Fédérale de Lausanne, EPFL (CH)

Abstract: In this brief, extraction methods are proposed for determining the essential parameters of double gate junction field-effect transistors (FETs). First, a novel method for determining free carrier effective mobility, similar to a recently proposed method for MOSFETs, is developed. The same method is then extended to cover also the case when series resistance is present, while series resistance itself may be determined from the measurement from two FETs with different channel lengths. The key technological and design parameter is the threshold voltage, which may be unambiguously determined from the transconductance-to-current ratio with a constant-current method. The new methods are shown to be effective over a wide range of technical parameters, using technology computer-aided design simulations.

Fig: Extraction of carrier mobility for DG JFETs in linear region at 300K 

a) corresponding output conductance gds and constituents ∂gds/∂Vds and 2Qsc,d/b, and 

b) extracted mobility for long- and moderate-length devices close agreement with the constant, nonfield-dependent mobility (μ = 826 cm2/Vs) used in the TCAD simulations.

Aknowlegement: This work was supported in part by the INNOVATION-EL-Crete Project under Grant MIS 5002772.