[paper] THz characterization and modeling of SiGe HBTs

Sebastien Fregonese, Marina Deng, IEEE member, Marco Cabbia, Chandan Yadav*, IEEE member, Magali De Matos, and Thomas Zimmer, Senior Member, IEEE

THz characterization and modeling of SiGe HBTs

review (invited)

IEEE J-EDS, 2020, pp.1-1 

DOI:10.1109/JEDS.2020.3036135

hal-03014869

IMS Laboratory, University of Bordeaux (F)
*Department of Electronics and Communication Engineering, National Institute of Technology Calicut (IN)

Abstract: This paper presents a state-of-art review of on-wafer S-parameter characterization of THz silicon transistors for compact modelling purpose. After, a brief review of calibration/deembedding techniques, the paper focuses on the on-wafer calibration techniques and especially on the design and dimensions of lines built on advanced silicon technologies. Other information such as the pad geometry, the ground plane and the floorplan of the devices under test are also compared. The influence of RF probe geometry on the coupling with the substrate and adjacent structures is also considered to evaluate the accuracy of the measurement, especially using EM simulation methodology. Finally, the importance of measuring above 110 GHz is demonstrated for SiGe HBT parameter extraction. The validation of the compact model is confirmed thanks to an EM-spice cosimulation that integrates the whole calibration cum deembedding procedure.

Fig: EM probe models based on Picoprobe GGB (a) 1 GHz -110 GHz, (b) WR5, (c) WR3 and d) WR2.2. In all models, white=coaxial insulator, gray=solder, yellow=metal.

A complete description of probe topology and technology is given in:

A. Rumiantsev et R. Doerner; RF Probe Technology: History and Selected Topics; IEEE Microw. Mag., vol. 14, no 7, p. 46‑58, Nov. 2013, DOI: 10.1109/MMM.2013.2280241

Aknowledgement: This work is partly funded by the French Nouvelle-Aquitaine Authorities through the FAST project. The authors also acknowledge financial support from the EU under Project Taranto (No. 737454). The authors would like to thank STM for supplying the silicon wafer.

[paper] Accurate diode behavioral model with reverse recovery

Stanislav Banáš^a,b, Jan Divína^b, Josef Dobeš^b, Václav Paňko^a

^aON Semiconductor, SCG Czech Design Center, Department of Design System Technology, 1. maje 2594, 756 61 Roznov pod Radhostem, Czech Republic

^bCzech Technical University in Prague, Faculty of Electrical Engineering, Department of Radioelectronics, Technicka 2, 166 27 Prague 6, Czech Republic

Solid-State Electronics

Volume 139, January 2018, Pages 31–38

https://doi.org/10.1016/j.sse.2017.10.034

Highlights:

• The complex robust time and area scalable Verilog-A model of diode containing reverse recovery effect has been developed.
• Due to implemented reverse recovery effect the model is useful especially for high-speed or high-voltage power devices.
• The model can be used as stand-alone 2-terminal diode or as a parasitic p-n junction of more complex lumped macro-model.
• Two methods of model parameter extraction or model validation have been demonstrated.

ABSTRACT: This paper deals with the comprehensive behavioral model of p-n junction diode containing reverse recovery effect, applicable to all standard SPICE simulators supporting Verilog-A language. The model has been successfully used in several production designs, which require its full complexity, robustness and set of tuning parameters comparable with standard compact SPICE diode model. The model is like standard compact model scalable with area and temperature and can be used as a stand-alone diode or as a part of more complex device macro-model, e.g. LDMOS, JFET, bipolar transistor. The paper briefly presents the state of the art followed by the chapter describing the model development and achieved solutions. During precise model verification some of them were found non-robust or poorly converging and replaced by more robust solutions, demonstrated in the paper. The measurement results of different technologies and different devices compared with a simulation using the new behavioral model are presented as the model validation. The comparison of model validation in time and frequency domains demonstrates that the implemented reverse recovery effect with correctly extracted parameters improves the model simulation results not only in switching from ON to OFF state, which is often published, but also its impedance/admittance frequency dependency in GHz range. Finally the model parameter extraction and the comparison with SPICE compact models containing reverse recovery effect is presented [read more...]

FIG: Solving the recursive calculation of reverse recovery charge

QUCS mentioned in IEEE-EDL paper

Jacopo Iannacci, Fondazione Bruno Kessler (FBK), Trento, Italy, has recently published an article in the IEEE Electron Device Letters (EDL) where he used and explicitly mentioned the QUCS, FOSS CAD/EDA simulator:

RF-MEMS Technology for Future Mobile and High-Frequency Applications:

Reconfigurable 8-Bit Power Attenuator Tested up to 110 GHz

J. Iannacci, M. Huhn, C. Tschoban and H. Pötter

in IEEE EDL, vol. 37, no. 12, pp. 1646-1649, Dec. 2016.

Abstract: In this letter, we present and test—to the best of our knowledge, for the first time—, an 8-bit (256-state) reconfigurable RF-MEMS attenuator, from 10 MHz up to 110 GHz, realized in the CMM-FBK technology. Resistive loads, in series and shunt configuration, are selectively inserted on the RF line by means of electrostatic MEMS ohmic switches. The network exhibits several attenuation levels in the range of −10/−45 dB that are rather flat up to 50 GHz, and a certain number of configurations with VSWR smaller than 4 from nearly dc up to 110 GHz, and better than 2 on a frequency span of ~80 GHz.

doi: 10.1109/LED.2016.2623328

[read more: http://ieeexplore.ieee.org/stamp/stamp.jsp?tp=&arnumber=7726036&isnumber=7739309]