Postdoc in Semiconductor Devices, and circuit design

Postdoc in Semiconductor Devices, and circuit design

Sønderborg, Denmark

We [sdu.dk] are seeking an enthusiastic new colleague as a PostDoc in the field of Semiconductor Devices, and circuit design. As a postdoc in our team, you will have the opportunity to contribute to cutting-edge research and innovation in this rapidly evolving field with a strong collaboration with international industry partners.

The position is located in the section of Electrical Engineering in Sønderborg within the Centre for Industrial Electronics (CIE). The Centre has currently approximately 30 faculty members including senior (full and associate professors), junior (assistant professors and postdocs), PhDs, and support staff. The task portfolio of the PostDocs will be linked to one main project and several smaller projects within CIE. CIE is embedded in a powerhouse in electronics, which includes researchers and developers at universities and industries on both sides of the Danish-German border. CIE is a new initiative striving for high quality and great impact of its research, innovation, and education. Central to achieving this objective is access to state-of-the-art facilities and collaborations with industries. In the semiconductor research group in CIE, we are a member of European projects and already settled our international collaborations with the pioneer industry.

The positions aim to build strong knowledge and competencies within the field of semiconductor devices, especially in the fields of wide band gap semiconductor devices, circuit design, failure mechanisms, and simulations.

Job description

• Conduct research in the field of WBG semiconductors with a focus on GaN and SiC devices.
• Innovate design structures through simulation-based approaches calibrated by experimental data.
• Apply TCAD simulation and design tools, build demonstrators, and verify your simulation by experimental measurements.
• Familiar with the fabrication process to realize devices in the clean room and explore their potential applications.
• Experimental characterization of devices (static and dynamic) to analyze the device behavior.
• Stay updated with the latest advancements in WBG semiconductor devices and contribute to the development of innovative solutions.
• You will be involved in the daily supervision of PhD, Master, and Bachelor students who perform research on similar topics.
• You will publish and present your work both at international conferences and in scientific journals with high impact.

Profile and requirements 

• Ph.D. in Electrical Engineering, Semiconductor Physics, or a related field.
• Strong background in theory and simulation of WBG semiconductor devices, device modeling, and circuit design.
• Hands-on experience in fabrication processes such as lithography, Mask design, etching, and deposition appreciated.
• Background in characterization techniques, failure mechanisms, and reliability tests.
• Ability to work independently as well as collaboratively in a research team.
• Strong communication skills to effectively present research findings and contribute to scientific discussions.
• Ability to publish in high-impact conferences and journals.

Starting date: March 2024.
Type of contract: Full-time
Employment: 2-year position

Further information is available from 

Professor Thomas Ebel, Head of CIE, phone: +45 93 50 72 05 

Associate Professor Samaneh Sharbati, phone: +45 65 50 82 60

Conditions of employment
Employment as a postdoc requires scientific qualifications at PhD level. Employment as a postdoc is temporary and will cease without further notice at the end of the period. The successful applicant will be employed in accordance with the agreement between the Ministry of Finance and the Danish Confederation of Professional Associations

The assessment process
Read about the Assessment and selection process. Shortlisting may be used.

Application procedure

• The application must be in English and must include:Motivated application
• Detailed Curriculum Vitae
• Certificates/Diplomas (MSc and PhD)
• List of publications, indicating the publications attached
• Examples of the most relevant publications. Please attach one pdf-file for each publication
• Reference letters and other relevant qualifications may also be included.

Formalities
Documents should not contain a CPR number (civil registration number) – in this case, the CPR number must be crossed out. The application and CV must not exceed 10 MB. If you experience technical problems, you must contact hcm-support@sdu.dk.

The application deadline is 20. February 2024 at 23.59.

Further information for international applicants about entering and working in Denmark.

Further information about The Faculty of Engineering.

The University of Southern Denmark wishes to reflect the surrounding community and therefore encourages everyone, regardless of personal background, to apply for the position.

[book] Future Ultra Low Power Electronics

Semiconductor Devices and Technologies for Future Ultra Low Power Electronics (1st ed.)

Nirmal, D., Ajayan, J., & Fay, P.J. (Eds.)

CRC Press. (2021).

DOI: 10.1201/9781003200987

Abstract: This book covers the fundamentals and significance of 2-D materials and related semiconductor transistor technologies for the next-generation ultra low power applications. It provides comprehensive coverage on advanced low power transistors such as NCFETs, FinFETs, TFETs, and flexible transistors for future ultra low power applications owing to their better subthreshold swing and scalability. In addition, the text examines the use of field-effect transistors for biosensing applications and covers design considerations and compact modeling of advanced low power transistors such as NCFETs, FinFETs, and TFETs. TCAD simulation examples are also provided. 

Contents:

Preface vii

Editors ix

Contributors xi

Chapter 1: An Introduction to Nanoscale CMOS Technology Transistors: A Future Perspective; pp: 1

Kumar Prasannajit Pradhan

Chapter 2: High-Performance Tunnel Field-Effect Transistors (TFETs) for Future Low Power Applications; pp: 29

Ribu Mathew, Ankur Beohar, and Abhishek Kumar Upadhyay

Chapter 3: Ultra Low Power III-V Tunnel Field-Effect Transistors; pp: 59

J. Ajayan and D. Nirmal

Chapter 4: Performance Analysis of Carbon Nanotube and Graphene Tunnel Field-Effect Transistors; pp: 87

K. Ramkumar, Singh Rohitkumar Shailendra, and V. N. Ramakrishnan

Chapter 5: Characterization of Silicon FinFETs under Nanoscale Dimensions; pp: 115

Rock-Hyun Baek and Jun-Sik Yoon

Chapter 6: Germanium or SiGe FinFETs for Enhanced Performance in Low Power Applications; pp: 129

Nilesh Kumar Jaiswal and V. N. Ramakrishnan

Chapter 7: Switching Performance Analysis of III-V FinFETs .; pp: 155

Arighna Basak, Arpan Deyasi, Kalyan Biswas, and Angsuman Sarkar

Chapter 8: Negative Capacitance Field-Effect Transistors to Address the Fundamental Limitations in Technology Scaling; pp: 187

Harsupreet Kaur

Chapter 9: Recent Trends in Compact Modeling of Negative Capacitance Field-Effect Transistors; pp: 203

Shubham Tayal, Shiromani Balmukund Rahi, Jay Prakash Srivastava, and Sandip Bhattacharya

Chapter 10 Fundamentals of 2-D Materials; pp: 227

Ganesan Anushya, Rasu Ramachandran, Raj Sarika, and Michael Benjamin

Chapter 11 Two-Dimensional Transition Metal Dichalcogenide (TMD) Materials in Field-Effect Transistor (FET) Devices for Low Power Applications; pp 253

R. Sridevi and J. Charles Pravin

Index pp: 289

[Foreword] Special Issue on Compact Modeling of Semiconductor Devices

Foreword

Special Issue on Compact Modeling of Semiconductor Devices

DOI: 10.1109/JEDS.2020.3039023

THIS Special Issue is dedicated to recent research in the field of compact modeling of semiconductor devices. This is the first J-EDS Special Issue on compact modeling. In the last years, a number of new semiconductor device structures, for electronic and photonic applications, have been developed. Compact models are needed for the incorporation of these new devices in integrated circuits. Therefore, a Special Issue was needed to present recent compact modeling solutions for semiconductor devices

A total of 8 regular papers and 2 invited papers have been accepted in this Special Issue. All papers, including the invited ones, were subjected to a thorough peer reviewing. A high number of reviewers participated in this process. This has resulted in a Special Issue containing very high-quality papers.  The published papers target compact modeling aspects for a wide number of devices, such as SiGe HBTs, IGBTs, SiC SB diodes, LDMOSFETs, Multi-Gate MOSFETs, RRAMs, TFET SRAMs, and organic TFTs. Open source Verilog-A compil- ing is also targeted by one paper. Different operation regimes and conditions are addressed: charging/discharging, THz, high power, tunneling radiation environments, . . . 

One invited paper, by U. Sharma and S. Mahapatra, addresses the modeling of HCD Kinetics for full VG/VD span under different experimental conditions across architectures and its SPICE implementation The other invited paper, by Fregonese et al., presents a review of THz characterization and modeling of SiGE HBTs.

I [BJ] would like to thank the work done by the rest of the Editors of this Special Issue and also by all the reviewers who participated in this process. And of course, I want to thank all the authors for their interest in submitting papers to this Special Issue. Thanks to authors, reviewers, and editors, this high-quality Special Issue has been possible.

BENJAMIN IÑIGUEZ, Guest Editor-in-Chief Department of Electronic, Electrical and Automatic Control Engineering University Rovira i Virgili 43007 Catalonia, Spain YOGESH SINGH CHAUHAN, Guest Associate Editor Department of Electrical Engineering Indian Institute of Technology Kanpur Kanpur 208016, India SLOBODAN MIJALKOVIC, Guest Associate Editor Simulation Group EDA Division Silvaco Europe Ltd. Cambridgeshire PE27 5JL, U.K. KEJUN XIA, Guest Associate Editor Department of Front End Innovation NXP Semiconductors Chandler, AZ 85224 USA

JUNG-SUK GOO, Guest Associate Editor Department of Compact Model Development GLOBALFOUNDRIES Inc. Santa Clara, CA 95054 USA MARCELO PAVANELLO, Guest Associate Editor Department of Electrical Engineering Centro Universitario FEI 09850-901 São Bernardo do Campo, Brazil MAREK MIERZWINSKI, Guest Associate Editor Department of PathWave Software and Solutions Keysight Technologies Santa Rosa, CA 95403 USA (e-mail: ) WLADEK GRABINSKI, Guest Associate Editor Department of Research and Development Modelling GMC Consulting 1291 Commugny, Switzerland

[paper] TFT for Mixed Signal and Analog Computation

Eva Bestelink, Olivier de Sagazan, Lea Motte, Max Bateson, Benedikt Schultes, S. Ravi P. Silva,

and Radu A. Sporea

Versatile Thin‐Film Transistor with Independent Control of Charge Injection and Transport

for Mixed Signal and Analog Computation

Adv. Intell. Syst.. (2020) pp.1-9, DOI:10.1002/aisy.202000199 

Abstract: New materials and optimized fabrication techniques have led to steady evolution in large area electronics, yet significant advances come only with new approaches to fundamental device design. The multimodal thin-film transistor introduced here offers broad functionality resulting from separate control of charge injection and transport, essentially using distinct regions of the active material layer for two complementary device functions, and is material agnostic. The initial implementation uses mature processes to focus on the device’s fundamental benefits. A tenfold increase in switching speed, linear input–output dependence, and tolerance to process variations enable low-distortion amplifiers and signal converters with reduced complexity. Floating gate designs eliminate deleterious drain voltage coupling for superior analog memory or computing. This versatile device introduces major new opportunities for thin-film technologies, including compact circuits for integrated processing at the edge and energy-efficient analog computation.

Figure: Outcomes of separating control for injection and conduction shown via TCAD simulation. a) MMT transient response is much faster than conventional contact-controlled TFTs

b) A MMT with multiple, appropriately sized CG1 gates can function as a digital-to-analog converter (DAC) with CG2 providing an enabling, sampleand-hold (S/H) function. 

Acknowledgements: E.B. and R.A.S. contributed equally to this work. This work was partly supported through EPSRC grants EP/R511791/1 and EP/R028559/1 and Research Fellowship 10216/110 from the Royal Academy of Engineering of Great Britain. Device fabrication had been performed on the NanoRennes platform. The authors thank Dr. Brice Le Borgne for initial liaison and process discussions, Prof. John M. Shannon for on-going advisory meetings, Prof. Craig Underwood for reviewing the manuscript, Dr. David Cox and Mr. Mateus Gallucci Masteghin for assistance with the SEM images.

[Call for Chapters] Sub-Micron Semiconductor Devices: Design and Applications

Call for Chapters

Title: Sub-Micron Semiconductor Devices: Design and Applications

Introduction: To follow Moore’s law, semiconductor devices are scaled-down without compromising the performance. Semiconductor devices are supposed to be reduced in dimensions and work at lower operating biases but the problem arises during the manufacturing of the devices. Thus, it is a dire necessity to opt for a solution that can help in continuing the path of performance improvement. Steady performance enhancement using optimization techniques can support the time required for advancements in fabrication technologies. This publication confines the novel semiconductor devices, issues with conventional devices, optimization techniques and solutions for the performance enhancement. Even with the presence of a vast amount of data regarding semiconductor devices, it is hard for a researcher to go through most of the recent advancements altogether and understand them in a clear way. The motive behind the book is to comprehensibly present the material related to the recent advancements in the field of semiconductor devices that can allow the reader to interpret the possible concepts behind the content. The study of novel semiconductor devices may help in unraveling the mystery behind the problems that are required to tackle during the fabrication of molecular devices.

Topics: [Not limited to the given topics but relevant topics will be considered as well]

• Basic of Scaled-Down Devices
• (Nano-FET, TFET, LED, Solar Cell, TFT, HEMT, Diodes, RTDs, Photodiode, Quantum-Dots, Spin-FET, etc.)
• Comparative Study of Novel Semiconductor Devices
• Inclusion of Quantum Effects in Nano-Devices
• (Short Channel Effects, Fermi-Level-Pinning, Quantum Confinement, Discrete DOS, etc.)
• Device Modelling and Physics
• (Analytical, Compact, NEGF, Quantum, Verilog, Spice, etc.)
• Novel Materials for Devices
• (Graphene, Silicene, TMDCs, Organic, Perovskite, 2D Materials, TCO, Photo-dielectric, etc.)
• Characterization and Fabrication
• (Spectroscopic, Microscopic, MBE, CVD, Spin-Coating, Defects, etc.)
• Optimization Techniques
• (Negative Capacitance, Feedback, Gate-on-Source, Dopingless, 2DEG, Schottky Contact, etc.)
• Testing of Semiconductor Devices
• Applications
• (Biosensor, Radiation Sensor, Light Sensor, Analog/Digital Circuit Applications, MEMS, etc.)
• Issues and Solutions of Novel devices
• Future Device Technology

Important Dates (Updated):

Chapter Proposal Submission: 10 September 2020 Notification of Acceptance: 15 September 2020 Full Chapter Submission: 25 October 2020

Review Result Returned: 30 October 2020 Final Acceptance: 10 November 2020 Publication of Book: January-February 2021

Submission:

Kindly submit the chapter proposal [Tittle, Abstract (500-1000 words), Possible Content, Author details] before the due date via E-mail at call.chapters.crc@gmail.com. Any kind of query regarding the chapter or abstract submission, formatting and corrections can be submitted to query.chapters.crc@gmail.com

Editors:

Ashish Raman¹, Deep Shekhar² and Naveen Kumar³

Electronics and Communication Engineering Department, Dr. B. R. Ambedkar National Institute of Technology Jalandhar, [Grand Trunk Road, Barnala - Amritsar Bypass Rd, Jalandhar, India 144011] 

Official E-mail IDs: ¹ ramana@nitj.ac.in, ² deeps.ec.18@nitj.ac.in, ³ naveenk.ec.16@nitj.ac.in