[paper] Compact Modeling in MFIS Negative-Capacitance FETs

N. Pandey and Y. S. Chauhan

Analytical Modeling of Short-Channel Effects in MFIS Negative-Capacitance FET

Including Quantum Confinement Effects

in IEEE TED (Early Access), DOI: 10.1109/TED.2020.3022002.

Abstract: An analytical 2-D model of double-gate metal-ferroelectric-insulator-semiconductor-negative-capacitance FET (MFIS-NCFET), using Green's function approach, in the subthreshold region, is presented in this article. The explicit solution of coupled 2-D Landau-Devonshire and Poisson equations is analytically derived. Subsequently, an analytical and explicit model of subthreshold slope is developed from potential functions. The developed model includes quantum-mechanical effects, which considers not only geometrical confinements but also electrical confinements. The analytical solution of a 2-D nonhomogeneous Poisson equation coupled with the 1-D Schrödinger equation is used to obtain the potential function in the channel. The impact of the ferroelectric thickness (tfe) on quantum confinement is also studied. We find that larger tfe reduces the quantum confinement effect. Therefore, as tfe increases, threshold voltage roll-off with the variation in Si-body thickness decreases.

Fig: Schematic of DG MFIS-NCFET.

Aknowegement: This work was supported in part by the Swarna Jayanti Fellowship under Grant DST/SJF/ETA-02/2017-18 and in part by the FIST Scheme of the Department of Science and Tech- nology under Grant SR/FST/ETII-072/2016. 

[paper] compact nanowire JAM-MOSFET model

Kamalaksha Baral, Prince Kr Singh, Sanjay Kumar, Manas Ranjan Tripathy,

Ashish Kr Singh, Sweta Chander and S JitA

2-D compact DC model for engineered nanowire JAM-MOSFETs 

valid for all operating regimes

Semiconductor Science and Technology, Vol. 35, No. 8

Abstract: This manuscript reports a 2-D compact analytical model for DC characteristics under all possible regimes of operations of a cylindrical gate (CG) nanowire junctionless accumulation mode (JAM) MOSFET including the effects of various device engineering techniques. Superposition technique with appropriate boundary conditions has been used to solve 2-D Poisson’s equation considering both free/accumulation and depletion charges. The minimum potential concept has been used to conceive the threshold voltage formulation considering the effects of structural and electrical quantum confinements. An optimized device model has been formulated incorporating various device engineering. The potential model could also be used for potential modeling of doped inversion mode MOSFETs. Complete drain current including gate induced drain leakage (GIDL) has been derived from the potential model. Drain current has been derived individually for different regions. Further the effects of temperature and trapped interface charges have been included in the model. A 3-D commercial TCAD has been used to validate the model results of our proposed device. 

Fig: A 2-D cross-sectional view of cylindrical gate nanowire
junctionless accumulation mode MOSFET 

[paper] InAs-OI-Si MOSFET Compact Model

S. K. Maity, A. Haque and S. Pandit

Charge-Based Compact Drain Current Modeling of InAs-OI-Si MOSFET 

Including Subband Energies and Band Nonparabolicity

in IEEE TED, vol. 67, no. 6, pp. 2282-2289, June 2020

doi: 10.1109/TED.2020.2984578

Abstract: In this article, we report a physics-based compact model of drain current for InAs-on-insulator MOSFETs. The quantum confinement effect has been incorporated in the proposed model by solving the 1-D Schrödinger–Poisson equations without using any empirical model parameter. The model accurately captures the variation of surface potential, charge density in the inversion layer, and subband energy levels with gate bias inside the quantum well. The conduction-band nonparabolicity effect on modification in eigen energy, effective mass, and density of states is derived and incorporated into the proposed model. The velocity overshoot effect that originates from the quasi-ballistic nature of carrier transport is also considered in the model. The proposed drain current model has been implemented in Verilog-A to use in the SPICE environment. The model predicted results are in good agreement with the commercial device simulator results and experimental data. 

Fig: Energy band profile of InAs-OI-Si MOSFET in the direction perpendicular to the oxide interface at flat-band condition. E0 and E1 denote the first and the second subband energy levels, respectively, and ΔEc and Vox represent the conduction-band offset between buffer-channel and oxide-channel regions, respectively.

Acknowledgment: The author S. Pandit would like to thank the Department of Electronics and Information Technology, Government of India for utilizing the resources obtained under the SMDP-C2SD Project at the University of Calcutta.

URL: https://ieeexplore.ieee.org/stamp/stamp.jsp?tp=&arnumber=9067014&isnumber=9098120