[mos-ak] [press note] 2nd MOS-AK India Conference at IIT Hyderabad Feb. 25-27, 2019

2019 IEEE International Conference on Modeling of Systems Circuits and Devices

Organised by Joint Chapter of CAS /ED Societies, IEEE Hyderabad Section

2nd MOS-AK India Conference (IEEE Conference #45395)

Venue: IIT Hyderabad February 25-27, 2019

The MOS-AK Compact Modeling Association, a global standardization forum for semiconductor device models, held its consecutive 2nd International IEEE MOS-AK India Conference 2019 between February 25-27, 2019 at the IIT Hyderabad. The 2nd International IEEE MOS-AK India Conference 2019 is the results of join, collaborative effort. The conference organization would not be possible without direct involvements and financial support provided directly by Collage and IIT Hyderabad as well as the MOS-AK distinguished industrial sponsors including: ams semiconductors, Rhode and Schwarz, Keysight, Synergy, Synopsys, Xilinx and SCL. The MOS-AK India Conference has  also drawn attention of the Joint Chapter of the CAS and EDS Societies of the IEEE Hyderabad Section which provided direct technical program cosponsorship. The Indian Electronic Semiconductor Association (IESA) as well as Swissnex India have provide pronounced dissemination support.

Inauguration session of 2nd International IEEE MOS-AK India Conference 2019 has been chaired by Prof. Mohammed Arifuddin Sohel, MJ College Hyderabad, who welcomed all MOS-AK participants and invited prominent guests Surinder Singh, Director, SCL;  Sebasties Hug, CEO and Consul General of Swissnex;  Sumohan Chenapayya, Dean R&D, IIT Hyderabad;  V. Hanuma Sai, Director, ams semiconductors India Pvt. Ltd.;  N. Venkatesh, Chair, IEEE Hyderabad Section;  Wladek Grabinski, MOS AK (EU);  P.A. Govindacharyulu, General Co Chair, MOS AK India 2019  to open  the 2nd MOS-AK/India Conference.

The MOS-AK India Conference program has been organized as three days scientific R&D event covering recent advances into the technology TCAD simulations, compact/SPICE modeling as well as the device level analog/RF and digital IC designs. The internationally renowned academic and industrial speakers and presenters have delivered 4 tutorial lectures [1-4], 7 keynote talks [5-11], 2 plenary talks [12-13] as well as 22 regular research papers. The MOS-AK Association is an open research forum adequately supporting all R&D activities. An open panel discussion was organized to review challenges and opportunities for women in engineering (WIE) [14]. The MOS-AK speakers shared their latest perspectives on compact/SPICE modeling and Verilog-A standardization in response to the dynamically evolving semiconductor industry and academic R&D efforts. The event featured advanced technical presentations covering compact model development, implementation, and deployment. Presented original unpublished works in all the topics related to the compact/SPICE modeling and its Verilog-A standardization will be submitted for further publication. The conference proceedings will be submitted to IEEE Explore. Best MOS-AK/India papers has been selected and awarded: Gold leaf [15], Silver leaf [16] and Bronze leaf [17] certificates, accordingly. Highest ranked paper authors from regular submission will be invited to extend their R&D contribution in the form of a book chapters in a book titled "Compact Modeling: Technology, Devices, IC Design" by River Publishers, the technical program promoter of MOS-AK/India 2019 Conference. These R&D topics have also received attention of local media and press [18-21]. For more information about each of the R&D contributions, go online to 2nd MOS-AK/India Conference

Photo: All the MOS-AK/India Conference participants at IIT Hyderabad

The MOS-AK Association plans to continue its standardization efforts by organizing future compact modeling meetings, workshops and courses arround the globe thru 2019 year, including:

• 4th Sino MOS-AK Workshop, Chengdu (CN) June 2019
• 17th MOS-AK at ESSDERC/ESSCIRC, Krakow (PL), Sept. 2019
• 12th International MOS-AK Workshop, Silicon Valley (US) Dec. 2019
• 3rd MOS-AK India Conference, Hyderabad, Feb. 2020

About MOS-AK Association:

MOS-AK, an international compact modeling association primarily focused in Europe, to enable international compact modeling R&D exchange in the North/Latin Americas, EMEA and Asia/Pacific Regions. The MOS-AK Modeling Working Group plays a central role in developing a common information exchange system among foundries, CAD vendors, IC designers and model developers by contributing and promoting different elements of compact/SPICE modeling and its Verilog-A standardization and related CAD/EDA tools including FOSS for the compact/SPICE models development, validation/implementation and distribution. For more information please visit: mos-ak.org

Tutorials:

[1] Dr. Charvaka Duvvury iT2 Technologies (USA) ESD on-chip protection design 

[2] Dr. Wladek Grabinski MOS-AK (EU) Verilog-A Standardization

[3] Weronika Zubrzycka, AGH, (PL) Radiation effect and Radiation hardening in devices 

[4] Prof. Roberto Murphy, INOE (MX) Characterization of Semiconductor Devices in the High Frequency Regime

Keynote Talks: 

[5] Prof. Yogesh Singh Chauhan, IIT Kanpur (IN) Negative Capacitance Transistors - Modeling, Simulation and Processor Performance

[6] Dr. Surinder Singh, Semiconductor Labs, Chandigarh  (IN), Chandigarh Research at SCL

[7] Weronika Zubrazycka, AGH, (PL) Radiation Effects on Circuits for Space and High-Energy Physics Applications - A case study 

[8] Madabusi Govindrajan, GLOBALFOUNDRIES, Bangalore (IN)  Challenges for RF modeling in the connected era 

[9] Dr. Usha Gogineni, Maxim Semiconductors (IN)  Compact Models for Analog and Mixed Signal Design 

[10] Prof. Santanu Mahapatra, IISc, Bangalore (IN)  Atom-to-Circuit modeling technique for emerging nanomaterial based MOSFETs 

[11] Prof. Gilson Wirth, UFRGS (BR) (Webinar) Charge Trapping Phenomena in MOSFETS: From Noise to Bias Temperature Instability 

Plenary Talks: 

[12] Prof. Jaijeet Roychowdhury, UC, Berkeley, USA Well-Posed Compact Modeling 

[13] Dr. Ehrenfried Seebacher, ams (A) Compact Modeling for Industrial Applications 

Panel Discussion: 

[14] Dr. G. Uma Devi, Director, NRSC, (IN): Challenges and opportunities for Women in Engineering (WIE). 

Best papers awards:

[15] Chithra and Nagendra Krishnapura, "Modeling Techniques for Faster Verification of a Time to Digital Converter System-on-Chip Design"

[16] Mohit Ganeriwala, Enrique Marin, Francisco Ruiz and Nihar Mohapatra," A Compact Charge and Surface Potential Model for III-V Quadruple-Gate FETs With Square Geometry"

[17] Suprava Dey, Tara Prasanna Dash, Chinmay Kumar Maiti, Jhansirani Jena, Eleena Mohapatra and Sanghamitra Das," Performance Evaluation of Gate-All-Around Si Nanowire Transistors with SiGe Strain engineering"

Headlines: 

[18] "Swiss interest in India's energy and tech fields" Date: Feb. 27,2019 Publication: The Hindu Edition: Hyderabad

[19] "IIT Hyderabad hosts MOS-AK India 2019 International Conference on Modeling of Systems Circuits and Devices" India Education diary  Edition: Online: Prof. Sushmee Badhulika 

[19] Indo-Swiss collaboration needed in education" Date: Feb. 27,2019 Publication: The New Indian express, Edition: Hyderabad

[20] "Switzerland looking forward to stronger ties with Telangana" Feb. 27,2019   Publication: Telangana Today, Edition:  Hyderabad

[21] "IIT Hyderabad hosts MOS-AK India 2019 International Conference on Modeling of Systems Circuits and Devices " Date: Feb. 27,2019 Publication: Andhra Jyothi Edition: Hyderabad pp:3

WG14032019

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[paper] Well-Posed Device Models for Electrical Circuit Simulation

Well-Posed Device Models for Electrical CircuitSimulation
A Guide to Creating Robust Device Models
A. Gokcen Mahmutoglu, Tianshi Wang, Archit Gupta and Jaijeet Roychowdhury
March 25, 2017

Synopsis: This document provides guidelines for creating computational device models that work well in simulation. We build our discussion around the mathematical notion of “well-posedness”. We show that the requirements for a model to be well-posed stem from the internal working mechanisms of simulators. Therefore, our main aim is to provide insight into the numerical procedures used by simulators in order to help model developers avoid ill-posedness issues. We start our discussion with an example that shows how an ill-posed Verilog-A model can produce different simulation results in different simulators. We then provide a step-by-step simulation case study. In this case study, we illustrate the role of device models in simulations by examining the steps a simulator goes through, from taking a netlist as input to producing a simulation result as output. Finally, we distill our discussion in a functional definition of a well-posed model. As an extension to our theoretical discussion, we also provide practical guidelines that should be followed by Verilog-A models in order to avoid ill-posedness issues [read more...]

This document is published as a part of the Nano-Engineered Electronic Device Simulation (NEEDS) initiative. NEEDS is an NSF-funded initiative whose charter includes the development of tools and techniques for the production of high-quality device models¹:
NEEDS has a vision for a new era of electronics that couples the power of billion-transistor CMOS technology with the new capabilities of emerging nano-devices and a charter to create high-quality models and a complete development environment that enables a community of compact model developers.

NEEDS Team: Purdue, MIT, UC Berkeley, and Stanford.”

¹For more information about NEEDS please visit https://nanohub.org/groups/needs/.

[paper] Bipolar and MOS Transistors Under the Effect of Radiation

Measurements of the Electrical Characteristics of Bipolar and MOS Transistors

Under the Effect of Radiation

K. O. Petrosyants, L. M. SamburskiiI. A. KharitonovM. V. Kozhukhov

Meas Tech (2017) doi:10.1007/s11018-017-1100-z

ABSTRACT: The specific nature of the process of measuring the electrical characteristics of bipolar and metal-oxidesemiconductor (MOS) transistors subjected to the action of neutron, electron, and gamma irradiation is considered. An automated measurement system is developed. Examples illustrating the use of the system for investigations of the radiation hardness of transistors are presented and the parameters of SPICE models for use in circuit design (including SOI/SOS CMOS circuits with EKV-RAD macromodel) are determined.

Translated from Izmeritel’naya Tekhnika, No. 10, pp. 55–60, September, 2016 [read more...]