[paper] Virtual N2 PDK

Yiying Liu , Minghui Yin , Huanhuan Zhou, Yunxia You, Weihua Zhang, Hongwei Liu, Chen Wang, Yajie Zou, and Zhiqiang Li

Virtual_N2_PDK: A Predictive Process Design Kit for 2-nm Nanosheet FET Technology

IEEE Transactions on Very Large Scale Integration (VLSI) Systems (2025)

DOI: 0.1109/TVLSI.2025.3529504

1 EDA Center, Institute of Microelectronics, Chinese Academy of Sciences, Beijing (CN)
2 School of Integrated Circuits, University of Chinese Academy of Sciences, Beijing (CN)
3 State Key Laboratory of Fabrication Technologies for Integrated Circuits, Beijing (CN)

Abstract: Nanosheet FETs (NSFETs) are considered promising candidates to replace FinFETs as the dominant devices in sub-5-nm processes. To encourage further research into NSFET-based integrated circuits, we present Virtual_N2_PDK, a predictive process design kit (PDK) for 2-nm NSFET technology. All assumptions are based on publicly available sources. Ruthenium (Ru) interconnects are employed for the buried power rail (BPR) and tight-pitch layers. Wrap-around contact (WAC) is also integrated into Virtual_N2_PDK to investigate its impact on circuit performance. By calibrating the BSIM-CMG model with 3-D technology computer-aided design (TCAD) electrothermal simulation results, SPICE models that account for self-heating effects (SHEs) are generated for devices with and without WAC. The simulation results show that with the WAC structure, the energy-delay product (EDP) of standard cells is reduced by an average of 25.18%, while the frequency of a 15-stage ring oscillator circuit increases by 26.05%.

FIG: 3D view of the NSFET structure and layouts of SRAM bit cells:
(b) 111 SRAM cell, (c) 112 SRAM cell, and (d) 122 SRAM cell.

Acknowledgements: This work was supported in part by the Strategic Priority Research Program of Chinese Academy of Sciences (CAS) under Grant XDA0330401 and in part by CAS Youth Interdisciplinary Team under Grant JCTD-2022-07.

[book] Nano Interconnects: Device Physics, Modeling and Simulation

Afreen Khursheed and Kavita Khare

Nano Interconnects: Device Physics, Modeling and Simulation

CRC Press; 1st edition (2021)

ISBN: ‎ 978-0367610487

This textbook comprehensively covers on-chip interconnect dimension and application of carbon nanomaterials for modeling VLSI interconnect and buffer circuits. It provides analysis of ultra-low power high speed nano-interconnects based on different facets such as material modeling, circuit modeling and the adoption of repeater insertion strategies and measurement techniques. It covers important topics including on-chip interconnects, interconnect modeling, electrical impedance modeling of on-chip interconnects, modeling of repeater buffer and variability analysis. Pedagogical features including solved problems and unsolved exercises are interspersed throughout the text for better understanding. Aimed at senior undergraduate and graduate students in the field of electrical engineering, electronics and communications engineering for courses on Advanced VLSI Interconnects, Advanced VLSI Design, VLSI Interconnects, VLSI Design Automation and Techniques, this book:

• Provides comprehensive coverage of fundamental concepts related to nanotube transistors and interconnects.
• Discusses properties and performance of practical nanotube devices and related applications.
• Covers physical and electrical phenomena of carbon nanotubes, as well as applications enabled by this nanotechnology.
• Discusses the structure, properties, and characteristics of graphene-based on-chip interconnect.
• Examines interconnect power and interconnect delay issues arising due to downscaling of device size.

[paper] 3nm Nano-Sheet FETs

Etienne SICARD* and Lionel TROJMAN**

Introducing 3-nm Nano-Sheet FET technology in Microwind

hal-03377556: Submitted on 14 Oct 2021

  

*INSA-Dgei, Toulouse (F)
**ISEP, Issy les Moulineaux (F)

Abstract: This paper describes the implementation of the novel Nano-sheet FET (NS-FET) for the 3-nm CMOS technology node in Microwind. After a general presentation of the electronic market and the roadmap to the atomic scale, design rules and basic metrics for the 3-nm node are presented. Concepts related to the design of NS-FET and design for manufacturing are also described. The performances of a ring oscillator, basic cells, sequential cells and a 6-transistor RAM memory are also analyzed.

Fig: A simple 3-stage ring oscillator based on compiled inverters “Fast” mode.

[ref] MICROWIND software allows the designer to simulate and design an integrated circuit at physical description level. Born in Toulouse (France), Microwind is an innovative CMOS design tool for educational market.