[book] Negative Capacitance Field Effect Transistors

Negative Capacitance Field Effect Transistors

Physics, Design, Modeling and Applications

Edited By Young Suh Song, Shubham Tayal, Shiromani Balmukund Rahi, Abhishek Kumar Upadhyay

Pages 63 Color & 7 B/W Illustrations

ISBN 9781032445311 176 Sept. 29, 2023 by CRC Press

Description

This book aims to provide information in the ever-growing field of low-power electronic devices and their applications in portable device, wireless communication, sensor, and circuit domains. Negative Capacitance Field Effect Transistor: Physics, Design, Modeling and Applications, discusses low-power semiconductor technology and addresses state-of-art techniques such as negative-capacitance field-effect transistors and tunnel field-effect transistors. The book is broken up into four parts. Part one discusses foundations of low-power electronics including the challenges and demands and concepts like subthreshold swing. Part two discusses the basic operations of negative-capacitance field-effect transistor (NC-FET) and Tunnel Field-effect Transistor (TFET). Part three covers industrial applications including cryogenics and biosensors with NC-FET. This book is designed to be one-stop guidebook for students and academic researchers, to understand recent trends in the IT industry and semiconductor industry. It will also be of interest to researchers in the field of nanodevices like NC-FET, FinFET, Tunnel FET, and device-circuit codesign.

Table of Contents

Chapter 1 Recent Challenges in IT and Semiconductor Industry: From Von Neumann Architecture to the Future

Young Suh Song, Shiromani Balmukund Rahi, Navjeet Bagga, Sunil Rathore, Rajeewa Kumar Jaisawal, P. Vimala, Neha Paras, K. Srinivasa Rao

Chapter 2 Technical Demands of Low-Power Electronics

Soha Maqbool Bhat, Pooran Singh, Ramakant Yadav, Shiromani Balmukund Rahi, Billel Smaani, Abhishek Kumar Upadhyay, Young Suh Song

Chapter 3 Negative capacitance Field Effect Transistors: Concept and Technology

Ball Mukund Mani Tripathi

Chapter 4 Basic Operation Principle of Negative Capacitance Field Effect Transistor

Malvika, Bijit Choudhuri, Kavicharan Mummaneni

Chapter 5 Basic Operational Principle of Anti-ferroelectric Materials and Ferroelectric Materials

Umesh Chandra Bind, Shiromani Balmukund Rahi

Chapter 6 Basic Operation Principle of Optimized NCFET: Amplification Perspective

S. Yadav, P.N Kondekar, B. Awadhiya

Chapter 7 Spin Based Magnetic Devices With Spintronics

Asif Rasool, Shahnaz kossar, R.Amiruddin

Chapter 8 Mathematical Approach for Future Semiconductor Roadmap

Shiromani Balmukund Rahi,Abhishek Kumar Upadhyay, Young Suh Song, Nidhi Sahni, Ramakant Yadav, Umesh Chandra Bind,Guenifi Naima,Billel Smaani,Chandan Kumar Pandey,Samir Labiod, T.S. Arun Samul,Hanumanl Lal, H. Bijo Josheph

Chapter 9 Mathematical Approach for Foundation of Negative Capacitance Technology

Shiromani Balmukund Rahi,Abhishek Kumar Upadhyay, Young Suh Song, Nidhi Sahni, Ramakant Yadav, Umesh Chandra Bind,Guenifi Naima,Billel Smaani,Chandan Kumar Pandey,Samir Labiod, T.S. Arun Samul,Hanumanl Lal, H. Bijo Josheph

[paper] NCFET CMOS Logic

Reinaldo Vega, Senior Member, IEEE, Takashi Ando*, Senior Member, IEEE,  

Timothy Philip, Member, IEEE

Junction Design and Complementary Capacitance Matching 

for NCFET CMOS Logic 

IEEE J-EDS 2021

DOI 10.1109/JEDS.2021.3095923

IBM Research, Albany, NY 12203

* IBM T.J. Watson Research Center, Yorktown Heights, NY 10598

Abstract: Negative capacitance field effect transistors (NCFETs) are modeled in this study, with an emphasis on junction design, implications of complementary logic, and device Vt menu enablement. Contrary to conventional MOSFET design, increased junction overlap is beneficial to NCFETs, provided the remnant polarization (Pr) is high enough. Combining broad junctions with complementary capacitance matching (CCM) in MFMIS (metal/ ferroelectric/ metal/ insulator/ semiconductor) NCFETs, it is shown that super-steep and non-hysteretic switching are not mutually exclusive, and that it is theoretically possible to achieve non-hysteretic sub-5 mV/dec SS over > 6 decades. In a CMOS circuit, due to CCM, low-Vt pairs provide steeper subthreshold swing (SS) than high-Vt pairs. Transient power/performance is also modeled, and it is shown that a DC optimal NCFET design, employing broad junctions, CCM, and a low-Vt NFET/PFET pair, does not translate to improved AC power/performance in unloaded circuits compared to a conventional FET reference. It is also shown that the same non-hysteretic DC design point is hysteretic in AC and may also lead to full polarization switching at higher voltages. Thus, a usable voltage window for AC NCFET operation forces a retreat from the DC-optimal design point.

Fig: Equivalent capacitance network and illustrative C-V curve showing NMOS and NC curves. CNC > CINV results in non-hysteretic switching, but low voltage gain in the off-state due to CNC >> COV. Setting CNC to CNC2, which is matched more closely to COV, results in very low SS, but also hysteretic switching as CNC2 < CINV. 

Acknowledgment: The authors would like to thank Paul Solomon and Prof. Sayeef Salahuddin for insightful discussions, as well as Synopsys for technical support.

[paper] Compact Modeling of NC FDSOI FETs

C. K. Dabhi, S. S. Parihar, A. Dasgupta and Y. S. Chauhan

Compact Modeling of Negative-Capacitance FDSOI FETs for Circuit Simulations

IEEE TED, vol. 67, no. 7, pp. 2710-2716, July 2020

DOI: 10.1109/TED.2020.2994018

Abstract: The compact model for negative capacitance FDSOI (NC-FDSOI) FET with metal–ferroelectric–insulator– semiconductor (MFIS) gate-stack is presented, for the first time, in this article. The model is developed based on the framework of BSIM-IMG, an industry-standard model (i.e., for zero thickness of a ferroelectric layer, the model mimics the behavior of BSIM-IMG). The developed NCFDSOI model is computationallyefficient and captures drain current and its derivatives accurately. The model shows an excellent agreement with numerical simulation and the measured data of NC-FDSOI FET. The proposed compact model is implemented in Verilog-A and tested for circuit simulations using commercial circuit simulators.

Fig: (a) Schematic of NC MFIS FDSOI FET - FE layer is sandwiched between the oxide layer and the top gate. (b) Gate-stack of MFIS FDSOI FET. (c) Gate-stack of MFMIS FDSOI FET.

Acknowledgment: This work was supported in part by the Swarnajayanti Fellowship and FIST Scheme of the Department of Science and Technology and in part by the Berkeley Device Modeling Center (BDMC). The authors would like to thank Dr. Sarvesh S. Chauhan for reading the manuscript and providing valuable feedback.

[paper] Physical Mechanisms of Reverse DIBL and NDR in FeFETs With Steep Subthreshold Swing

C. Jin, T. Saraya, T. Hiramoto and M. Kobayashi,

in IEEE J-EDS, vol. 8, pp. 429-434, 2020

doi: 10.1109/JEDS.2020.2986345

Abstract - We have investigated transient IdVg and IdVd characteristics of ferroelectric field-effect transistor (FeFET) by simulation with ferroelectric model considering polarization switching dynamics. We show transient negative capacitance (TNC) with polarization reversal and depolarization effect can result in sub-60mV/dec subthreshold swing (SS), reverse drain-induced barrier lowering (R-DIBL), and negative differential resistance (NDR) without traversing the quasi-static negative capacitance (QSNC) region of the S-shaped polarization-voltage (PV) predicted by single-domain Landau theory. Moreover, the mechanisms of R-DIBL and NDR based on the TNC theory are discussed in detail. The results demonstrated in this work can be a possible explanation for the mechanism of previously reported negative capacitance field-effect transistor (NCFET) with sub-60mV/dec SS, R-DIBL, and NDR.

Equivalent circuits of a ferroelectric capacitor in both static and transient conditions.