[C4P] NEWCAS 2024

The 22nd IEEE International NEWCAS Conference

Sherbrooke, Quebec, Canada

June 16-19, 2024.

The NEWCAS Conference will reflect the wide spectrum of topics, research and practice in the field of circuits and systems and offer an international forum for exchanging ideas and results. There will also be tutorials, special sessions and keynote talks by prominent experts on current topics in microsystems research.

The NEWCAS Topics Include, but Are Not Limited to:

 

Analog/mixed-signal circuits Biomedical circuits and systems Digital circuits and systems Communications circuits and systems RF & microwave circuits Photonic integrated circuits CAD and design tools Test and verification Energy harvesting and power management Low-power low-voltage Microsystems and embedded systems Circuits and systems for AI algorithms

Neural networks and neuromorphic circuits Sensory circuits and systems Imaging and image sensors Emerging technologies and technology trends Microsystems and embedded systems Circuits and systems for AI algorithms Neural networks and neuromorphic circuits Sensory circuits and systems Imaging and image sensors Emerging technologies and technology trends Quantum computing

AUTHORS SCHEDULE

• DEADLINE for full paper submission: February 1, 2024
• DEADLINE for tutorial and special sessions proposals: February 1, 2024
• NOTIFICATION of acceptance: April 4, 2024
• SUBMISSION DEADLINE of Final manuscript: May 1, 2024

For detailed information on proposal and paper submission procedure, please refer to the conference website: newcas2024.org

[C4P] 82nd DRC

DRC 2024 

The 82nd Device Research Conference

The University of Maryland, College Park

2024.DEVICERESEARCHCONFERENCE.ORG

DRC will be held in coordination with the Electronic Materials Conference (EMC), which will occur the same week, from June 26-28. This recognizes the strong interaction between device and electronic materials research and provides fruitful exchanges of information between attendees of both Conferences.

The 2024 Conference will feature:

• An informative, timely short course in rapidly developing fields
• Oral and poster presentations on electronic/photonic device experiments 
• and simulations
• Plenary and invited presentations given by worldwide leaders
• Evening rump sessions
• Strong student participation and Student Paper Awards
• Focus Sessions on Devices for Neuromorphic Computing
• More than 50 invited speakers covering a wide spectrum of devices

Topics to be presented include:

Devices for Biological and Healthcare Applications Emerging Devices Devices for Extreme Conditions Spintronic and Magnetic Devices Memory Devices Modeling and Simulation of Devices Nanoscale and Vacuum Devices Optoelectronic and Optical Devices

Power Devices Quantum Devices Heterogeneously Integrated Devices Thin-Film and Flexible Devices RF and Terahertz Devices Wide-bandgap Device 2D Materials and Devices Neuromorphic Computing Devices

Important Dates

• Feb. 16, 2024 Abstract Submission Deadline
• April 5, 2024 Acceptance Notification
• April 10, 2024 Registration Opens
• May 15, 2024 Early Bird Registration Deadline

[C4P] 50th ESSERC, Sept. 9-12. 2024, Bruges (BE)

CALL FOR PAPERS

https://www.esserc2024.org/papers

The aim of ESSERC (European Solid-State Electronics Conference) is to provide an annual European forum for the presentation and discussion of recent advances in solid-state devices and circuits. It is a continuation of the past ESSDERC-ESSCIRC conferences. The level of integration for system-on-chip design is rapidly increasing. This is made available by advances in semiconductor technology. Therefore, more than ever before, a deeper interaction among technologists, device experts, IC designers and system designers is necessary. 

ESSERC is governed by a Steering Committee and consists of Plenary Keynote Presentations, invited papers and session on technology, circuits and joint papers bridging both device and circuit communities, respectively. 

PAPERS SUBMISSION DEADLINE: APRIL 5, 2024

Papers submitted for review must clearly state:

• The purpose of the work
• How and to what extent it advances the state-of-the art
• Specific results and their impact

Only work that has not been previously published or submitted elsewhere will be considered. Submission of a paper for review and subsequent acceptance is considered as a commitment that the work will not be publicly available prior to the conference. Measurement results or calibration against measured data is required to support the claims of the submitted paper.

After selection of papers, the authors will be informed about the decision of the Technical Program Committee by e-mail by 24 May 2024.

At the same time, the complete program will be published on the conference website. An oral presentation will be given at the Conference for each accepted paper. No-shows will result in the exclusion of the papers from any conference related publication. The submitted final PDF files should be IEEE Xplore compliant.

For each paper independently, at least one (co-)author is required to register for the Conference (one registration one paper policy). Registration fees and deadlines will be soon available

CONFERENCE TRACKS (although not limited, papers are solicited for the following main topics):

1. Advanced Technology, Process and Materials
2. Analog, Power and RF Devices
3. Compact Modeling and Process/Device Simulation
   
   TCAD and advanced simulation techniques and studies, compact/ SPICE modeling of electronic, optical, organic, emerging, and hybrid devices and their IC implementation and interconnection. Verilog-A models of semiconductor devices (including bio/ med sensors, MEMS, microwave, RF, high voltage and power, emerging technologies, and novel devices), parameter extraction, reliability and variability, performance evaluation and open-source benchmarking/implementation methodologies. Modeling of interactions between process, device and circuit design, design/technology co-optimization, foundry/fabless interface strategies. Numerical, analytical, statistical modeling and simulation of electronic, optical and hybrid devices, interconnect, isolation, and 2D/3D integration. Simulations of material properties and fabrication processes. Advanced physical phenomena (quantum mechanical and non-stationary transport phenomena, ballistic transport). Mechanical and/or electro-thermal modeling and simulation. Simulations of reliability aspects of materials and devices.
4. Analog Circuits
5. Data Converters
6. RF & mm-Wave Circuits
7. Frequency Generation Circuits
8. Digital Circuits & Systems
9. Power Management
10. Wireless Systems
11. Wireline and Optical Circuits and Systems
12. Emerging Computing Devices and Circuits
13. Architectures and Circuits for AI and ML
14. Devices & Circuits for Sensors, Imagers and Displays

WHY BRUGES?

Bruges is a place that lives and breathes history. Visiting this historic city means travelling back in time to the Middle Ages. It is both magical and authentic. Brugge in medieval times was known as a commercial metropolis in the heart of Europe. 

Bruges is one of Europe’s best-preserved cities, evidenced by the fact that its historic city center has been designated an UNESCO World Heritage Site. The iconic spires of its cathedral and bell tower, its cobbled streets, winding canals and whitewashed façades are almost painfully picturesque.

In the 15th century, Brugge was the cradle of the Flemish Primitives and a center of patronage and painting development for artists such as Jan van Eyck and Hans Memling. Many of their works were exported and influenced painting styles all over Europe. Exceptionally important collections have remained in the city until today. Travelers from all over the world are coming to Belgium to visit Bruges.

[C4P] LAEDC 2024

CALL FOR PAPERS & POSTERS

LAEDC 2024 R&D topics of interest include, but are not limited to:

All electron-based devices Electron Devices for Quantum Computing RF-MMW-5G Semiconductor-, MEMS- and Nanotechnologies Packaging, 3D integration Sensors and actuators Display technology Modeling and simulation Reliability and yield Device characterization Reliability Agrivoltaics

Flexible electronics Biomedical Devices Circuit-device interaction Novel materials and process modules Technology roadmaps Electron device engineering education Electron device outreach Optoelectronics, photovoltaic and photonic devices and systems Humanitarian Projects STEM Initiatives Energy harvesting 2D Materials and Devices

IMPORTANT DATES:

• Paper submission deadline: January 15, February 19, 2024
• Author notification: April 1, 2024
• LAEDC Conference Dates: MAY 8-10 2024

SPECIAL SESSIONS:

• MOS-AK Workshop
• IEEE EDS MQ
• LAEDC Summer School
• IEEE WIE/YP Session
• Humanitarian Technology Session

ABOUT GUATEMALA:

Guatemala, country of Central America. The dominance of an Indigenous culture within its interior uplands distinguishes Guatemala from its Central American neighbours. The origin of the name Guatemala is Indigenous, but its derivation and meaning are undetermined. Some hold that the original form was Quauhtemallan (indicating an Aztec rather than a Mayan origin), meaning “land of trees,” and others hold that it is derived from Guhatezmalha, meaning “mountain of vomiting water” - referring no doubt to such volcanic eruptions as the one that destroyed Santiago de los Caballeros de Guatemala (now Antigua Guatemala), the first permanent Spanish capital of the region’s captaincy general. The country’s contemporary capital, Guatemala City, is a major metropolitan centre. Quetzaltenango, in the western highlands, is the nucleus of the Indigenous population.

[Call for Book Chapters] Perovskite Solar Cells

Call for Book Chapters:

Book Title: Perovskite Solar Cell

Table of Content

• Introduction to Perovskite Solar Cells
• Fundamentals of Perovskite Materials
• Fabrication Techniques
• Characterization Methods
• Perovskite Solar Cell Physics

Important Dates:

Chapter proposal submission deadline: 15th November 2023
Notification of Acceptance: 21st November 2023
Full Chapter submission: 30th January 2024
Acceptance/Rejection Notification: 10th February 2024

Prospective authors are requested to submit their chapter proposals/full chapters. 

<https://www.routledge.com/our-customers/authors/publishing-guidelines>

There are no publication fees for a chapter submitted to this book publication. All submitted chapters will be peer reviewed. For chapter proposals/full chapter submission and queries: tdsubash2007@gmail.com

[C4P] 17th ITC at the University of Surrey

FIRST CALL FOR PAPER

The 17th International Thin-Film Transistor Conference (ITC2022) is dedicated to TFT related technologies for displays, sensors and general large area and flexible electronics. As TFT applications broaden and expand beyond traditional markets, the 17th ITC will provide a platform for sharing the research progress and discussing the challenges in this field. It will be between 14-16 September, hybrid format, online and on site at the University of Surrey (UK).

Areas of Interest include, but are not limited to:

• Semiconductor materials and processing for high performance TFTs
• Understanding and addressing instabilities of TFTs
• TFT based functional devices (e.g., sensors, memories, synapse)
• Scaling of TFTs for high resolution integration
• TFT compact models for circuit simulation
• TFT backplane integration for displays and sensors
• Flexible and stretchable TFT devices and circuits
• Circuit design and implementations of TFTs

Student Fee Waiver: Top student submissions will be awarded a full registration fee waiver (in person or online), supported by EPSRC Project ALPACA teamsporea.info/alpaca/. Visit the conference website for instructions on how to be considered

Important Dates:

• 17 May 2022 Two-page Abstract Submission Deadline
• 28 June 2022 Notification of Acceptance
• 19 July 2022 Registration Opens
• 14-16 September 2022 Conference dates

For further information, please visit: itc2022.net

[ESSDERC/ESSCIRC 2022] Call for Papers

Paper submission is open!

Submission deadline: Apr 12, 2022 23:59 (GMT -0700)

Decision notification: May 31, 2022 23:59 (GMT -0700)

The aim of ESSCIRC and ESSDERC is to provide an annual European forum for the presentation and discussion of recent advances in solid-state devices and circuits. The level of integration for system-on- chip design is rapidly increasing. This is made available by advances in semiconductor technology. Therefore, more than ever before, a deeper interaction among technologists, device experts, IC designers and system designers is necessary. While keeping separate Technical Program Committees, ESSCIRC and ESSDERC are governed by a common Steering Committee and share Plenary Keynote Presentations and Joint Sessions bridging both communities. Attendees registered for either conference are encouraged to attend any of the scheduled parallel sessions, regardless to which conference they belong.

PAPER SUBMISSION
Manuscript guidelines as well as instructions on how to submit electronically will be available on this website. Papers must not exceed four A4 pages with all illustrations and references included.

THE PAPERS SUBMISSION DEADLINE: APRIL 12, 2022

Papers submitted for review must clearly state:

•The purpose of the work

•How and to what extent it advances the state-of-the art

•Specific results and their impact

Only work that has not been previously published or submitted elsewhere will be considered. Submission of a paper for review and subsequent acceptance is considered as a commitment that the work will not be publicly available prior to the conference. After selection of papers, the authors will be informed about the decision of the Technical Program Committee by e-mail by 31 May 2022.

At the same time, the complete program will be published on the conference website. A binary feedback (accepted/rejected) with no comments will be provided to the authors. An oral presentation will be given at the Conference for each accepted paper. No-shows will result in the exclusion of the papers from any conference related publication. The submitted final PDF files should be IEEE Xplore compliant.

[C4P] Special Issue on Advances in Sensor Devices for Biomedical Monitoring

International Journal of High Speed Electronics and Systems

ISSN (print): 0129-1564 | ISSN (online): 1793-6438

Call for Papers

Special Issue on Advances in Sensor Devices for Biomedical Monitoring

A biosensor is an analytical device, used for the detection of a chemical substance, that combines a biological component with a physicochemical detector. The sensitive biological element, e.g., tissue, microorganisms, organelles, cell receptors, enzymes, antibodies, nucleic acids, etc., is a biologically derived material or biomimetic component that interacts with, binds with, or recognizes the analyte under study. The transducer or the detector element, which transforms one signal into another one, works in a physicochemical way: optical, piezoelectric, electrochemical, electrochemiluminescence etc., resulting from the interaction of the analyte with the biological element, to easily measure and quantify. This special issue invites new strategies, innovative technologies, and algorithms to showcase the development in Sensor Devices for Biomedical Monitoring

The topic of interest includes the following:

• Biomedical sensors for Persuasive Monitoring
• Application of AI in biomedical sensor technology
• Devices embedded in Biosensors for biomedical Monitoring
• Automation in sensory devices for biomedical Monitoring
• Impact of Digitization on development of Biosensors.
• Flexible mechanics and electronic sensing devices for biomedical Monitoring
• Translucent and elastic sensors for biomedical Monitoring
• Automated Cell identification devices in biosensors for biomedical Monitoring
• Impact of Silk fibroin substrate in the development of Biosensor
• Study on Polymer electronic skin as Biosensor
• Review and comparative study in Biosensor

Important Dates:

Paper Submission Deadline: February 25, 2022

Author Notificatione: May 05, 2022

Revised Papers Submissione: July 15, 2022

Final Acceptancee: September 27, 2022

Guest Editorial Team:

Dr. Carlos Enrique Montenegro Marin

District University Francisco José de Caldas,

Bogotá, Colombia

Dr. Dinesh Jackson Samuel

Oxford Brookes University,

Oxford OX3 0BP, United Kingdom

Dr. Nallappan Gunasekaran

Shibaura Institute of Technology,

Saitama 337-8570, Japan.

[C4P] SISPAD 2021, September 27-29

International Conference on Simulation of Semiconductor Processes and Devices

SISPAD 2021, September 27-29

The abstract submission deadline April 9th.

Two-page abstract (text and figures, A4, 10 – 12 pt, pdf) should be sent to <sispad2021@utdallas.edu>  Authors of accepted papers are requested to submit a four-page final paper which will be published in the conference proceedings. The deadline for submission of the four-page final paper is July 9, 2021.

The SISPAD conference series provides an open forum for the presentation of the latest results and trends in process and device simulation. The conference is the leading forum for Technology Computer-Aided Design (TCAD) and is held alternatingly in the United States, Japan, and Europe in September.

Original contributions are solicited for SISPAD 2021 on topics that include but are not limited to:

• Modeling and simulation of established semiconductor device, including FinFETs, GAA FETs, ultra-thin SOI devices, optoelectronic devices, TFTs, sensors, power electronic devices, and organic electronic devices.
• Modeling and simulation of emerging devices including tunnel FETs, SETs, spintronic devices, straintronic devices, bio-electronic devices, and new material-based devices for various applications
• Modeling and simulation of interconnects, including noise and parasitic effects
• Modeling and simulation of all sorts of semiconductor processes, including first principles material design, and growth simulation of nano-scale fabrication
• Advances in fundamental aspects of device modeling and simulation, including of charge, spin, and thermal transport, of collective states including spin/magnetic and charge, and of fluctuation, noise, and reliability.
• Numerical methods and algorithms, including grid generation, user-interface, and visualization
• Compact modeling for circuit simulation, including low-power, high frequency, and power electronics applications
• Process/device/circuit co-simulation in context with system design and verification, including for emerging devices
• Modeling and simulation of equipment, topography, lithography
• Benchmarking, calibration, and verification of simulators

[C4P] MIXDES 2021 Paper Submission Deadline: 15 March 2021

MIXDES 2021 regular paper submission deadline is upcoming . As current COVID pandemic situation is still uncertain, the conference will be organized in hybrid mode or fully online. To help you with preparation of excellent papers, we have decided to move the submission deadline to 15 March 2021. As in previous year we are going to give you an opportunity to publish extended versions of your conference papers in Energies Journal. The information about the postMIXDES publication will be provided soon at the conference site (www.mixdes.org).

Important dates:

Conference days: 24-26 June 2021

Paper submission deadline: 15 March 2021

Notification of acceptance: 26 April 2021

Final paper versions: 17 May 2021

Mariusz Orlikowski - MIXDES 2021 Conference Secretary

[C4P] Spintronics-Devices and Circuits

Call for Papers for a Special Issue of 

IEEE Transactions on Electron Devices on

“Spintronics-Devices and Circuits”

Submission deadline: 30 September, 2021 

Publication date: April 2022

Spintronics is one of the emerging fields for the next-generation nanoscale devices offering better memory and processing capabilities with improved performance levels. It demonstrates great potential in the post-Moore era. Ever since the discovery of Giant Magneto-Resistance (GMR) effect in 1988, spintronics has shown rapid progress. Recent advances have expanded this technology to the entire electronics industry of sensors, memories, oscillators, quantum information processors, computer architecture, brain inspired computing and various other fields. Spintronics is now one of the most researched areas and is on the verge of becoming a mainstream technology. A hard disk drive (HDD) invented by IBM in 1956, now has a global market revenue of approximately $12bn. Other emerging field of application for this technology is magnetic field sensors that showcased a market revenue of ~$19b in 2018. The magnetic memory production at major foundries such as Samsung, Globalfoundries, Western Digital and TSMC marks the adoption of spintronics technology. However, in order to meet the ever-increasing demands of the industry, innovation in terms of modeling, design, materials, processes, circuits and applications are required. This Special Issue of the IEEE Transactions on Electron Devices will feature the most recent developments and the state-of-the-art in the field of spintronic devices, circuits and new architectures for high performance.

Topics of interest include, but are not limited to:

Materials:

Ferromagnets, Antiferromagnets, 2D material for better spin manipulation and spin logic devices, Heusler alloys, dilute magnetic semiconductors (DMS), half-metallic ferromagnet (HMF)

Transport mechanism:

Spin accumulation, injection and detection in spin devices, spin pumping techniques, angular momentum transportation by spin polarized currents, spin waves, magnons, spin hall effect, spin transfer torque, enhancement in spin diffusion length and coherence time

Spintronics devices:

STT-MRAM, SOT-MRAM, VCMA-MRAM, domain-wall, skyrmions, nano-oscillators, sensors etc. Low power and high-speed switching schemes for spintronic devices.

Optoelectronics and Spintronics:

All-optical switching of magnetization, inverse magnetooptical effects, single shot optical switching, modeling circuit and architecture level design for ultra-fast laser excitation

Memories:

High storage density MRAM, enhancement in power efficiency and speed

In-memory computing:

Spintronics based in-memory computing/ processing circuits/architectures and applications

Quantum Computing:

Quantum information processing, protocol for communication, computation and sensing, algorithms, spin qubit, systems and applications, spintronics-based quantum memories

Neuromorphic computing:

Hardware implementation of neural networks, analog and digital, architectures and applications

Fabrication:

Fabrication and characterization of novel materials and devices, hybrid spintronics integration and fabrication

Spintronics based circuits:

Reconfigurable and programmable spintronics based circuits, Security applications including RNG and PUF, ADC/DAC, reliability and power performance analysis of spintronics based devices and circuits

Submission instructions: Please visit the following link to download the templates:
http://www.ieee.org/publications_standards/publications/authors/author_templates.html
In your cover letter, please indicate that your submission is for this special issue.
Submission site: https://mc.manuscriptcentral.com/ted

The papers must present original material that has not been copyrighted, published or accepted

for publications in any other archival publications, that is not currently being considered for

publications elsewhere, and that will not be submitted elsewhere while under considerations

by the Transactions on Electron Devices.

Guest Editors:

1. Prof. Brajesh Kumar Kaushik, Department of Electronics and Communication Engineering, Indian Institute of Technology Roorkee, INDIA (Lead Guest Editor)

2. Dr. Sanjeev Aggarwal, Everspin Technologies Inc., USA

3. Prof. Supriyo Bandyopadhyay, Department of Electrical and Computer Engineering, VCU College of Engineering, USA

4. Prof. Debanjan Bhowmik, Department of Electrical Engineering, Indian Institute of Technology Delhi, INDIA

5. Dr. Vivek De, Circuits Research Lab, Intel, USA

6. Dr. Bernard Dieny, SPINTEC, IRIG/CEA Grenoble, FRANCE

7. Prof. Wang Kang, School of Microelectronics, Beihang University, CHINA

8. Prof. S.N. Piramanayagam, School of Physical & Mathematical Sciences - Division of Physics & Applied Physics, Nanyang Technological University, SINGAPORE

9. Prof. Kaushik Roy, School of Electrical and Computer Engineering, Purdue

University, USA

10. Prof. Ashwin A. Tulapukur, Department of Electrical Engineering, Indian Institute of Technology Bombay, INDIA

[C4P] New simulation methodologies for next-generation TCAD

Call for Papers for a Special Issue of

IEEE Transactions on Electron Devices on

"New simulation methodologies for next-generation TCAD" 

Submission deadline: February 28, 2021 

Publication date: November 2021

Technology Computer Aided Design is used to simulate semiconductor processes and devices,a field which has become increasingly complex and heterogeneous. Processing of integrated circuits requires nowadays over 400 process steps, and the resultant devices often have a complicated 3D structure and contain various materials. The full device behavior can only be understood by considering effects on all length scales from atomistic (interfaces, defects etc.) over nanometric (quantum confinement, non-bulk properties etc.) to full chip dimensions (strain, heat transport etc.), and time scales from femtoseconds to seconds. Voltages, currents and charges have been scaled to such low levels that electronic noise, statistical effects and process variations have a strong impact. Devices based on new materials (e.g. 2D crystals) and physical principles (ferroelectrics, magnetic materials, qubits etc.) challenge standard TCAD approaches. While the simulation methods developed by the physics community can describe the basic device behavior, they often lack important simulation capabilities like, for example, transient simulations or integration with other TCAD tools and are too slow for daily use. Due to the complexity of semiconductor technology, it becomes more and more difficult to assess the impact of a change in processing or device structure on circuit performance by looking at a single aspect of an isolated device under idealized conditions. Instead a TCAD tool chain is required that can handle realistic device structures embedded in a chip environment. New methodologies are required for all aspects of TCAD to ensure an efficient tool chain covering from atomistic effects to circuit behavior based on flexible simulation models that can handle new materials, device principles and the ensuing large-scale simulations.

This Special Issue of the IEEE Transactions on Electron Devices will feature the most recent developments and the state of the art in the field of TCAD for processing and for device behavior with a focus on new methodologies that improve the tool chain. Papers must be new and present original material that has not been copyrighted, published or accepted for publications in any other archival publications, that is not currently being considered for publications elsewhere, and that will not be submitted elsewhere while under considerations by the Transactions on Electron Devices.

Topics of interest include, but are not limited to:
• Artificial Intelligence applied to TCAD

• TCAD device models for
• new materials (2D materials, oxides, organic semiconductors, oxide semiconductors,
nanowire devices etc.)
• new device types (magnetic devices, memristors, spintronics, qubits, sensors etc.)
• physical effects (ferroelectric dielectrics, thermal transport at nanoscale, atomistic
simulation etc.)
• simulation conditions that push the limits of standard TCAD: ballistic transport, THz
frequencies, cryogenic conditions, device degradation, electromagnetic and plasma
waves in active devices, transient simulations, noise and fluctuations, microscopic 
simulation of large power devices

• Process simulation

• Atomistic process simulation to generate structures for atomistic device simulations
(including both interconnects and transistors)
• Gate stack modeling including dipole diffusion
• Stress simulation for nanosheet and forksheet devices and stress simulations
including layout effects
• Topological simulation
• Equipment simulation

• New methods for the TCAD tool chain

• Self-consistent integration of simulation models into the hierarchy
• Device-circuit interaction
• Multi-physics and multi-scale integration
• Efficient use of the data produced along the chain
• Workflow improvements
• Methods that improve the turn-around-time for TCAD simulations

Submission instructions: Manuscripts should be submitted in a double column format
using an IEEE style file. Please visit the following link to download the templates:
http://www.ieee.org/publications_standards/publications/authors/author_templates.html
In your cover letter, please indicate that your submission is for this special issue.

Guest Editors:

1. Prof. Fabrizio Bonani, Politecnico di Torino, Italy
2. Dr. Stephen Cea, Intel Corp., USA
3. Prof. Elena Gnani, University of Bologna, Italy
4. Prof. Sung-Min Hong, GIST, Republic of Korea
5. Dr. Seonghoon Jin, Samsung, USA
6. Prof. Christoph Jungemann, RWTH Aachen, Germany
7. Prof. Xiaoyan Liu, Peking University, China
8. Dr. Victor Moroz, Synopsys, USA
9. Dr. Anne Verhulst, imec, Belgium

[C4P] ICMTS: April 12 - 15, 2021

34th International Conference on Microelectronic Test Structures

ICMTS: April 12 - 15, 2021

Crowne Plaza Cleveland at Playhouse Square, Cleveland, OH, USA

Looking for the best opportunity to present and discuss your ideas and results about test structures, measurements and characterization? This is your chance! Join the 34th ICMTS conference. A Tutorial Short Course will precede the main conference. Several of the best measurement, equipment design, and manufacturing experts, will participate in the equipment exhibition and presentations. The conference will bring together designers and users of test structures to discuss recent developments and future directions, in a one-track program, with convivial breaks allowing attendees to discuss and exchange viewpoints and challenges. A Best Paper award will be presented by the Technical Program Committee. The IEEE Electron Devices Society is the co-sponsor, and all presented papers will be submitted for possible inclusion on IEEE Xplore®. Original papers are solicited presenting new developments in topics relevant to ICMTS, including but not limited to, test structures, measurements, and results, in the following areas:

• Design
• Methodologies, verification
• Within-die circuits for process characterization/monitoring
• Design enablement – Characterization and validation of digital and analog libraries
• Measurement techniques
• DC, AC and RF measurements: setup, test and analysis
• Reliability test - including thermal stability, failure analysis etc.
• Statistical analysis, variability, throughput increase, smart test strategies
• Use of machine learning and AI in analysis of data sets - parameter extraction etc.
• Wafer probing, within-die measurements, in-line metrology
• Throughput, testing strategies, yield enhancement and process control tests
• Applications
• Emerging memory technologies (single cell, arrays, and application in neural networks)
• Emerging transistor technologies for digital/analog/power applications
• Photonic devices - silicon integration, new displays (OLED, µ-displays)
• Flexible electronics and sensors (organic and inorganic materials)
• M(N)EMS, actuators, sensors, PV cells and other emerging devices

The author’s abstract submission consists of up to four pages in PDF format (font-embedded). The first page should include a title, a 50-word summary, author name(s), full address, contact number, and e-mail of the lead author, and any preference for oral or poster session presentation. The body of the abstract should consist of one page of text (800 to 1000 words) and up to two pages of major figures and tables. The selection process will be based on the technical merit and will be highly weighted in favor of abstracts with high test structure content (including illustration) along with measurements and data analysis.

The abstract submission deadline is November 6, 2020.

Abstracts can be submitted via the ICMTS website http://www.icmts.net using the “Submit Abstract” link on the front page. Notice of paper acceptance will be sent to the selected authors by mid-January, 2020, with instructions for the expanded manuscript preparation for the conference proceedings. The deadline for submission of the final paper will be March 17, 2021. 

Please join the ICMTS group at www.linkedin.com/groups/3804498, if you have in interest all things test structure related.

Details of the venue, hotel, registration, etc. will be posted at the ICMTS official web site. ICMTS is currently planned to be in person with the possibility of going virtual if necessary.

For further technical information, please contact the technical program chair:Chadwin Young, University of Texas at Dallas.

General Chair:

Brad Smith NXP Semiconductors

Technical Program Chair:

Chadwin Young University of Texas, Dallas

Tutorial Chair:

Matthew Rerecich Samsung Austin Semiconductor, LLC

Equipment Exhibition Chair:

Garrett Tranquillo Celadon Systems, Inc.

Local Arrangements:

Brad Smith NXP Semiconductors

ICMTS Steering Committee:

Asian Representative:

Satoshi Habu Keysight Technologies, Japan

European Representative:

Hans Tuinout NXP Semiconductors

USA Representative:

Bill Verzi Semiconductor Test Advisor

Special IJHSES Issue on Advancements in Smart Grid Technologies

International Journal of High Speed Electronics and Systems

ISSN (print): 0129-1564 | ISSN (online): 1793-6438

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Call for Papers

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Special Issue on Advancements in Smart Grid Technologies

This special issue is on electrical power generation, transmission, distribution and utilization in smart grid, from the viewpoints of individual power system elements and their integration, interaction and technological advancement.

The special issue focuses on microelectronic systems, circuits, power control and soft computing techniques in smart grid. It includes, but are not limited to, the following:

• Renewable & Sustainable Energy Technologies
• Cloud-assisted smart grid architectures and development
• Internet-centric smart grid solutions
• Case studies on recent advances in smart grid and renewable energy system
• Information and communication technology for enhancing smart grid and renewable energy system
• Future of renewable energy sources in environmental protection
• Sustainable computational methods to evaluate the optimization of renewable energy systems
• Networking and data mining in smart grids for continuous sustainable development
• Threat, challenges & opportunity of integrating smart grid and renewable energy system
• Generation techniques ranging from advances in conventional electromechanical methods, through nuclear power generation, to renewable energy generation.
• A study on the smart grid and renewable energy system for reducing the complexity of power grids
• Distribution techniques, equipment development, and smart grids.
• Renewable power generation and clean energy technologies
• Distributed energy resources and storage
• Modern power grid devices, sensors and wireless technologies

Paper Submission and Review Schedule:

• First announcement: October. 12th 2020
• Submission Deadline: November30th 2020
• Final notification: January 10, 2020
• Publication Date: June 30th 2020

Camera ready articles should be sent to the Guest Editor for consideration. Please specify the research topic on the cover page.

IJHSES Editor-in-Chiefs:
Michael Shur, Rensselaer Polytechnic Institute (USA)
Wladek Grabinski, MOS-AK (EU)

Guest Editor:
Naresh Kumar Yadav, D.C.R.U.S.T, Murthal (India)

[Call for Chapters] Sub-Micron Semiconductor Devices: Design and Applications

Call for Chapters

Title: Sub-Micron Semiconductor Devices: Design and Applications

Introduction: To follow Moore’s law, semiconductor devices are scaled-down without compromising the performance. Semiconductor devices are supposed to be reduced in dimensions and work at lower operating biases but the problem arises during the manufacturing of the devices. Thus, it is a dire necessity to opt for a solution that can help in continuing the path of performance improvement. Steady performance enhancement using optimization techniques can support the time required for advancements in fabrication technologies. This publication confines the novel semiconductor devices, issues with conventional devices, optimization techniques and solutions for the performance enhancement. Even with the presence of a vast amount of data regarding semiconductor devices, it is hard for a researcher to go through most of the recent advancements altogether and understand them in a clear way. The motive behind the book is to comprehensibly present the material related to the recent advancements in the field of semiconductor devices that can allow the reader to interpret the possible concepts behind the content. The study of novel semiconductor devices may help in unraveling the mystery behind the problems that are required to tackle during the fabrication of molecular devices.

Topics: [Not limited to the given topics but relevant topics will be considered as well]

• Basic of Scaled-Down Devices
• (Nano-FET, TFET, LED, Solar Cell, TFT, HEMT, Diodes, RTDs, Photodiode, Quantum-Dots, Spin-FET, etc.)
• Comparative Study of Novel Semiconductor Devices
• Inclusion of Quantum Effects in Nano-Devices
• (Short Channel Effects, Fermi-Level-Pinning, Quantum Confinement, Discrete DOS, etc.)
• Device Modelling and Physics
• (Analytical, Compact, NEGF, Quantum, Verilog, Spice, etc.)
• Novel Materials for Devices
• (Graphene, Silicene, TMDCs, Organic, Perovskite, 2D Materials, TCO, Photo-dielectric, etc.)
• Characterization and Fabrication
• (Spectroscopic, Microscopic, MBE, CVD, Spin-Coating, Defects, etc.)
• Optimization Techniques
• (Negative Capacitance, Feedback, Gate-on-Source, Dopingless, 2DEG, Schottky Contact, etc.)
• Testing of Semiconductor Devices
• Applications
• (Biosensor, Radiation Sensor, Light Sensor, Analog/Digital Circuit Applications, MEMS, etc.)
• Issues and Solutions of Novel devices
• Future Device Technology

Important Dates (Updated):

Chapter Proposal Submission: 10 September 2020 Notification of Acceptance: 15 September 2020 Full Chapter Submission: 25 October 2020

Review Result Returned: 30 October 2020 Final Acceptance: 10 November 2020 Publication of Book: January-February 2021

Submission:

Kindly submit the chapter proposal [Tittle, Abstract (500-1000 words), Possible Content, Author details] before the due date via E-mail at call.chapters.crc@gmail.com. Any kind of query regarding the chapter or abstract submission, formatting and corrections can be submitted to query.chapters.crc@gmail.com

Editors:

Ashish Raman¹, Deep Shekhar² and Naveen Kumar³

Electronics and Communication Engineering Department, Dr. B. R. Ambedkar National Institute of Technology Jalandhar, [Grand Trunk Road, Barnala - Amritsar Bypass Rd, Jalandhar, India 144011] 

Official E-mail IDs: ¹ ramana@nitj.ac.in, ² deeps.ec.18@nitj.ac.in, ³ naveenk.ec.16@nitj.ac.in

[C4P] ESSDERC TRACK3 Compact Modeling

European ESSDERC/ESSCIRC conference will be organized in Grenoble (F) on Sept.14-18, 2020 with its integral TRACK3: Compact Modeling and Process/Device Simulation which is open for submissions, now. You and all your R&D partners are welcome to submit a modeling paper. The paper submission deadline is April 17, 2020

TRACK3: Compact modeling and process/device simulation (including TCAD and advanced simulation techniques and studies)  focuses on following domains among other R&D topics:

• Compact/SPICE modeling of electronic, optical, organic, and hybrid devices and their IC implementation and interconnection. 
• Verilog-A models of the semiconductor devices (including Bio/Med sensors, MEMS, Microwave, RF, HV and Power, emerging technologies and novel devices)
• Compact/SPICE parameter extraction
• Performance evaluation and open source (FOSS) benchmarking/implementation methodologies
• Modeling of interactions between process, device and circuit design, 
• Foundry/Fabless interface strategies
• Numerical TCAD, analytical, statistical modeling and simulation of electronic, optical and hybrid devices, interconnect, isolation and 2D/3D integration
• Aspects of materials, fabrication processes and devices e.g. advanced physical phenomena (quantum mechanical and non-stationary transport phenomena, ballistic transport, ...)
• Optical, mechanical or electro-thermal modeling and simulation
• DfM, ageing, reliability of materials and devices

Please share our TRACK3 C4P with all your academic and industrial R&D partners active in the compact/SPICE modeling, Verilog-A standardization and TCAD/EDA simulations. Of course, your and your research team proactive contribution to our TRACK3 is more than welcome. I do hope that despite of a last minute notice, with your help, we will be able to draw even more attention to the ESSDERC/ESSCIRC Conference and, in particular, our modeling TRACK3

-- ESSDERC TRACK3 TPC

C4P Special Issue JEDS on Compact Modeling

Call for papers for a Special Issue
of IEEE Journal of the Electron Devices Society
on “Compact Modeling of Semiconductor Devices”
Submission deadline: April 1, 2020 MAY 15, 2020

In order to exploit the full potential of semiconductor devices in circuit design, compact device models are critically needed. Compact device models are the vehicle that allow the design of circuits using the targeted devices. Predictive and physically-based compact device models are required to accelerate development cycles and tackle issues of device efficiency, manufacturing yield and product stability. The performance/accuracy of the design software is dependent on the availability of accurate compact device models. 

Compact models should accurately capture the physics of the device in all operation regimes, but at the same time they should also have an analytical or semi-analytical formulation to be used in automated design tools for the simulation of circuits containing several or many devices. Furthermore, compact models can also be used as a tool to make realistic estimations of the performances of future devices following technological trends.

The lack of adequate compact models for a number of emerging devices is mostly due to the insufficient understanding of the physical phenomena which determine their behaviors. Regarding many emerging non-silicon devices, circuit and system designers very often rely on empirical behavioral macro-models and/or use existing silicon device compact models based on the conventional understanding of transport processes. However, for these emerging non-silicon devices, neither approach provides a fully adequate device description under all operation conditions, and therefore does not allow accurate production quality design.

Suggested topics include but not limited to:

1. Silicon MOSFET modeling

a. Advanced Bulk MOSFETs

b. SOI MOSFETs

c. Multi-Gate MOSFETs: Double-Gate MOSFETs, Surrounding-Gate MOSFETs, FinFETs, nanosheet MOSFETs, UTB SOI MOSFETs, etc.

d. Junctionless MuGFETs

e. Power and high voltage MOSFETs

2. Junction-based and compound semiconductor FET modeling:

a. Advanced MESFETs

b. Advanced HEMTs

c. III-V and III-N MOSFETs

d. Advanced JFETs

3. Diode and bipolar transistor modeling:

a. Advanced BJTs

b. HBTs

c. IGBTs

d. pn and pin diodes

e. Varactors

4. Emerging transistor modeling:

a. Tunnel FETs

b. Molecular transistors

c. Single Electron Transistors

d. Quantum Dot Transistors

e. Negative Capacitance Transistors

5. Emerging semiconductor devices

Memories, MRAM, PCRAM, etc.

Memristors

Spintronic devices

Layered/2D semiconductor devices

Graphene-based devices

6. TFT

a. a-Si:H TFTs

b. Polycrystalline Si TFTs

c. OTFTs and OECTs

d. Oxide TFTs

e. Single-crystal TFts

7. Modeling of physical effects

a. Noise

b. High frequency operation

c. Cryogenic conditions

d. Mismatch

e. Strain

f. High energy particle interactions in ICs (Cosmic rays and energy beams)

g. ESD events

h. Ballistic and quasi-ballistic transport

i. Layout dependent effects

8. Photonic devices

a. LEDs and OLEDs

b. Photodiodes

c. Solar cells

d. Photodetectors

e. SPADs

f. Photonic Crystals

9. Parameter extraction methods

a. Direct extraction methods

b. Global optimization methods

Submission instructions: Manuscripts should be submitted in a double column format using an IEEE style file. Please, visit https://ieeeauthorcenter.iece.org/create-your-ieee- article/use-authoring-toolsand-ieee-article-templates/ieee-article-templates/templates-for- transactions/ to download the templates. When submitting your manuscript through the IEEE’s web-based ScholarOne Author Submission and Peer Review System (https://mc.manuscriptcentral.com/jeds), please indicate that your submission is for this special issue.

Guest Editor in Chief:

• Benjamin Iniguez, Universitat Rovira i Virgili, Tarragona, Spain

Guest Associate Editors:

• Yogesh Chauhan, IIT Kanpur (IN) 
• Slobodan Mijalkovic, Silvaco Europe Ltd., St.Ives (UK) 
• Kejfun Xia, NXP Semiconductors, Phoenix, AZ (USA) 
• Jhung-Suk Goo, Global Foundries, Sunnyvale, CA (USA), 
• Marcelo Pavanello, Centro Universitario da FEI, Sao Paulo (BR), 
• Marek Mierzwinski, Keysight Technologies, Santa Rosa, CA (USA)
• Wladek Grabinski, GMC Consulting, Commugny (CH)

Please, direct all communications to Marlene James at m.james@ieee.org

DOI 10.1109/TED.2019.2960953

[C4P] EuroSOI-ULIS April 1-3, 2019, Grenoble (F)

5th Joint International EUROSOI and ULIS Conference

at Minatec, Grenoble (F) 

on April 1-3, 2019

The Conference Committee hopes that you will actively participate by submitting high quality papers and will enjoy the conference. The Conference Technical Digest will be published by IEEE and will be available online through IEEE Xplore. The abstract submission deadline is January 15, 2019.

Invited Speakers:

• Dr. Ionut RADU, SOITEC : "SOI technology: from niche to mainstream applications"
• Dr. Anabela VELOSO, IMEC: "Nanowire for ultra-scaled, high-density logic and memory applications"
• Dr. Marc GAILLARDIN, CEA: "Radiation effects in innovative devices"
• Prof. Ru HUANG, Peking University: "Steep slope devices"

More information are provided in the attached 2nd C4P and on the Conference website

MIXDES 2016 Paper Submission Deadline

MIXDES Paper Submission Deadline
(March 1st, 2016)

---------- Forwarded message ----------
From: MIXDES 2016 Organizing Committee

Dear Colleagues,

I would like to kindly remind you that paper submission for MIXDES 2016 Conference has been already opened. The deadline for regular paper submission is March 1st, 2016, so I encourage you to register your papers. The instruction for paper preparation is available online. Please note that the paper format and content may be still updated up to Final Paper Version deadline (May 31st, 2016).

This year the MIXDES 2016 Conference will take place in Lodz, Poland, June 23-25, 2016. For more information regarding the conference please visit the MIXDES 2016 Conference web site at
www.mixdes.org.

If you have any questions please do not hesitate to contact me.

Hoping to see you in Lodz,

Mariusz Orlikowski
Secretary of the 23rd International Conference
"Mixed Design of Integrated Circuits and Systems"
MIXDES 2016
http://www.mixdes.org