Yiying Liu , Minghui Yin , Huanhuan Zhou, Yunxia You, Weihua Zhang, Hongwei Liu, Chen Wang, Yajie Zou, and Zhiqiang Li
Virtual_N2_PDK: A Predictive Process Design Kit for 2-nm Nanosheet FET Technology
IEEE Transactions on Very Large Scale Integration (VLSI) Systems (2025)
DOI: 0.1109/TVLSI.2025.3529504
1 EDA Center, Institute of Microelectronics, Chinese Academy of Sciences, Beijing (CN)
2 School of Integrated Circuits, University of Chinese Academy of Sciences, Beijing (CN)
3 State Key Laboratory of Fabrication Technologies for Integrated Circuits, Beijing (CN)
Abstract: Nanosheet FETs (NSFETs) are considered promising candidates to replace FinFETs as the dominant devices in sub-5-nm processes. To encourage further research into NSFET-based integrated circuits, we present Virtual_N2_PDK, a predictive process design kit (PDK) for 2-nm NSFET technology. All assumptions are based on publicly available sources. Ruthenium (Ru) interconnects are employed for the buried power rail (BPR) and tight-pitch layers. Wrap-around contact (WAC) is also integrated into Virtual_N2_PDK to investigate its impact on circuit performance. By calibrating the BSIM-CMG model with 3-D technology computer-aided design (TCAD) electrothermal simulation results, SPICE models that account for self-heating effects (SHEs) are generated for devices with and without WAC. The simulation results show that with the WAC structure, the energy-delay product (EDP) of standard cells is reduced by an average of 25.18%, while the frequency of a 15-stage ring oscillator circuit increases by 26.05%.
FIG: 3D view of the NSFET structure and layouts of SRAM bit cells:
(b) 111 SRAM cell, (c) 112 SRAM cell, and (d) 122 SRAM cell.
(b) 111 SRAM cell, (c) 112 SRAM cell, and (d) 122 SRAM cell.
