[paper] Virtual N2 PDK

Yiying Liu , Minghui Yin , Huanhuan Zhou, Yunxia You, Weihua Zhang, Hongwei Liu, Chen Wang, Yajie Zou, and Zhiqiang Li

Virtual_N2_PDK: A Predictive Process Design Kit for 2-nm Nanosheet FET Technology

IEEE Transactions on Very Large Scale Integration (VLSI) Systems (2025)

DOI: 0.1109/TVLSI.2025.3529504

1 EDA Center, Institute of Microelectronics, Chinese Academy of Sciences, Beijing (CN)
2 School of Integrated Circuits, University of Chinese Academy of Sciences, Beijing (CN)
3 State Key Laboratory of Fabrication Technologies for Integrated Circuits, Beijing (CN)

Abstract: Nanosheet FETs (NSFETs) are considered promising candidates to replace FinFETs as the dominant devices in sub-5-nm processes. To encourage further research into NSFET-based integrated circuits, we present Virtual_N2_PDK, a predictive process design kit (PDK) for 2-nm NSFET technology. All assumptions are based on publicly available sources. Ruthenium (Ru) interconnects are employed for the buried power rail (BPR) and tight-pitch layers. Wrap-around contact (WAC) is also integrated into Virtual_N2_PDK to investigate its impact on circuit performance. By calibrating the BSIM-CMG model with 3-D technology computer-aided design (TCAD) electrothermal simulation results, SPICE models that account for self-heating effects (SHEs) are generated for devices with and without WAC. The simulation results show that with the WAC structure, the energy-delay product (EDP) of standard cells is reduced by an average of 25.18%, while the frequency of a 15-stage ring oscillator circuit increases by 26.05%.

FIG: 3D view of the NSFET structure and layouts of SRAM bit cells:
(b) 111 SRAM cell, (c) 112 SRAM cell, and (d) 122 SRAM cell.

Acknowledgements: This work was supported in part by the Strategic Priority Research Program of Chinese Academy of Sciences (CAS) under Grant XDA0330401 and in part by CAS Youth Interdisciplinary Team under Grant JCTD-2022-07.

[paper] Fast and Expandable ANN-Based Extraction

Jeong, HyunJoon, SangMin Woo, JinYoung Choi, HyungMin Cho, Yohan Kim,

Jeong-Taek Kong, and SoYoung Kim

Fast and Expandable ANN-Based Compact Model and Parameter Extraction for Emerging Transistors IEEE Journal of the Electron Devices Society (2023)

DOI 10.1109/JEDS.2023.3246477

Abstract: In this paper, we present a fast and expandable artificial neural network (ANN)-based compact model and parameter extraction flow to replace the existing complicated compact model implementation and model parameter extraction (MPE) method. In addition to nanosheet FETs (NSFETs), our published ANN based compact modeling framework is easily extended to negative capacitance NSFETs (NC-NSFETs), which are attracting attention as next-generation devices. Each device is designed using a technology computer-aided design (TCAD) simulator. Using device structure parameters, temperature, and channel doping depth as input variables, we construct a dataset of electrical properties used for machine learning (ML)-based modeling. The accuracy of predicting device electrical characteristics with the proposed ANN-based compact model is less than a 1% error compared to TCAD, and simulation results of digital and analog circuits using the proposed compact model show less than a 3% error. This allows the ANN-based modeling framework to achieve accurate DC, AC, and transient simulations without restrictions on device technology. In particular, temperature and process variables such as channel doping depth, which are not defined in the compact model parameters, are easily added to the previously presented five key parameters. Instead of conventional complex compact modeling and MPE work, we propose a method to create fast, accurate, flexible, and expandable ML-based Verilog-A SPICE models with design technology co-optimization (DTCO) capabilities.

Fig A: Conventional model parameter extraction flow

Fig B: The proposed ANN-based model parameter extraction flow

Acknowledgments: We thank the reviewers for improving the contents of the paper. This work was supported by an Institute of Information & communications Technology Planning & Evaluation (IITP) grant funded by the Korean government (MSIT) (No.2021-0- 00754, Software Systems for AI Semiconductor Design) and by a National Research Foundation of Korea grant funded by the Korean government (MISP) (NRF-2020R1A2C1011831). The EDA tool was supported by the IC Design Education Center (IDEC), Korea