[paper] Zener diode compact modeling and simulation

Mike Brinson

Modelling and simulation of Zener diode noise in the time domain

International Journal of Numerical Modelling Electronic Networks Devices and Fields

January 2023

DOI: 10.1002/jnm.3090

1 Centre for Communications Technology, London Metropolitan University, London, UK.

Abstract: This paper presents a new time domain Zener diode compact model for transient noise simulation. SPICE2 and SPICE3 use piece-wise linear time dependent sources for generating complex waveforms. This approach is not practical when applied to randomly generated noise. Today, through on-going improvements to freely available Circuit simulation tools, SPICE noise generation has moved to a new level. Ngspice, for example, computes white Gaussian noise ‘on-the-fly' as transient Simulation progresses. The proposed model has a simple behavioral structure that supports time domain shot, flicker, and thermal noise. The physical properties of the proposed model are introduced in the second section. This is followed by an evaluation of model performance in the third and fourth sections, including static DC, dynamic Charge, and transient noise characterization. Finally, the fifth section summarizes the conclusions of the research.

FIG: QuCS-S/Ngspice Zener diode behavioural model: subcircuit schematic drawing; intermediate equations and limexp function definition.

DATA AVAILABILITY STATEMENT: Data Sharing not applicable to this article as no datasets were generated or analyzed during the current study.

IEEE EDS Distinguished Lecturer by ED Poland Chapter

IEEE EDS Distinguished Lecturer by ED Poland Chapter

Krzysztof Górecki and Daniel Tomaszewski

EDS Distinguished Lecturer, Professor Mansun Chan (UST, Hong Kong) gave a talk titled “Simulation and Modeling of Dynamic Systems with Time Varying Device Characteristic” on May 21, 2019, at Łukasiewicz Research Network—Institute of Electron Technology (Łukasiewicz ITE), Warsaw, Poland. Approximately 15 persons from ITE and from abroad, traveled to Warsaw for the ESSDERC paper selection meeting and to attend the lecture.

The abstract of the Distinguished Lecture: The existing circuit simulation methodologies are based on time-invariant device models, electrical characteristics and parameters of which do not change over time. However, more recently, many new applications such as neuromorphic computing or artificial neural-network circuits require the use of devices with history dependent behavior. Due to such a behavior different from traditional transistors, which are the focus for the compact modeling community, a new approach to monitor the time dependent characteristics of these devices is necessary. In addition, a new simulation methodology is also required to predict the behavior of such system efficiently. In the presentation, a new approach to simulate dynamic systems was introduced. The proposed approach combined with the modification of simulation flow and compact model construction was introduced. The approach is very general and can be used to cover a wide class of devices with dynamic behavior such as memory function or device performance degradation during a prolonged operation.

A Mini-Colloquium was organized by the ED Poland Chapter in cooperation with: Gdynia Maritime University, Gdynia, Poland, Łukasiewicz Research Network—Instytut Technologii Elektronowej (Łukasiewicz-ITE), Warsaw, Poland, and a Department of Microelectronics and Computer Science, Lodz University of Technology, Lodz, Poland. Approximately 20 persons attended the full-day event. Nine interesting talks were presented by internationally recognized experts in the area of nanoelectronics, including three EDS Distinguished Lecturers (DLs).

Prof. Shinichi Takagi (The University of Tokyo) presented a talk “Tunneling FET technology for ultra-low power logic applications” addressing critical issues, technical challenges and viable technologies of TFETs using a variety of semiconductors such as Si, Ge and oxide semiconductors. Device engineering indispensable in improving the performance of TFETs were summarized with emphasis on the source junction formation technology and the optimal material design. The electrical characteristics of TFETs using Si and Ge homo junctions, Ge/strained SOI hetero-junctions and ZnO/(Si, Ge) hetero-junctions were presented as the viable examples.

Prof. Andrzej Strójwąs (PDF Solutions, and Carnegie Mellon University) had a talk “New Product Introduction Challenges in the Bleeding Edge Technology Nodes,” presenting a comprehensive methodology and a full suite of process-design design interaction characterization techniques to enable cost-effective introduction of new products in the 7 nm and below technologies.

Dr. Arkadiusz Malinowski (GlobalFoundries) gave a talk “Will FinFET era last only for 10 years? FinFET scaling challenges for next CMOS technology nodes,” in which challenges related to FinFET metrology/inspection, lithography/overlay, integration/variability, cycle time and cost were addressed.

Dr. Rajiv V. Joshi (DL, IBM Research Division Yorktown Heights) presented a lecture “Variability aware design in nm era.” He highlighted predictive analytical technique based on statistical analysis methodology targeting both memory and custom logic design applications is highlighted. Design case studies both in planar and non-planar technologies were discussed. Finally, the speaker discussed an efficient statistical methodology based on simulation and modeling to evaluate and minimize the aging of memory chips.

Prof. Henryk M. Przewłocki (DL, Łukasiewicz Research Network—ITE Warsaw) presented a talk “Expanding the horizon of photoelectric investigations of the MIS system properties,” in which he discussed an extended theory of the photocurrent vs. gate voltage characteristics, at different wavelengths of light illuminating the structure under test, with diffusion currents taken into account. The theory is in agreement with the relevant experimental characteristics. This opens the possibilities of developing new measurement methods of the MIS system crucial parameters.

Prof. Marcelo Pavanello (DL, Centro Universitario FEI) presented a talk “Performance and modeling of Nanowire-based MOSFETs.” He discussed differences between double-gate, triple-gate and nanowire-based MOSFETs and their characteristics. Also junctionless nanowire transistors (JNTs) were introduced as one of the interesting alternatives for downscaling because of their relative process simplicity compared with inversion-mode nanowires. Different aspects of modeling of the JNT steady-state and dynamic operation was interestingly presented.

Dr. Farzan Jazaeri (EPFL) presented a talk “Cryogenic Electronics and Quantum Computing Architecture.” He made an interesting review of topics of a quantum computation that holds the promise to solve problems that are intractable even for the most powerful supercomputers. Quantum computers process the information stored in quantum bits (qubits). The information in the qubits is fragile, so the qubits must be typically cooled to cryogenic temperature. Spin qubits in silicon were reported that have already been proposed and experimentally demonstrated in academic research laboratories.

Prof. Mike Brinson (London Metropolitan University) presented a talk “Equation-Defined template and synthesis driven compact modelling of semiconductor devices.” He reported current research that links Equation-Defined Device modelling with Verilog-A modules, driven by code templates and synthesis, which in turn result in an improved interactive modelling techniques. Throughout the talk a series of compact device models were introduced to demonstrate the fundamentals and application of the new approach to compact device modelling.

Dr. Władek Grabiński (DL, MOS-AK and GMC) presented a talk “FOSS tools for support of IC modeling and design with special emphasis on Verilog-A standardization.” He discussed selected FOSS CAD tools along complete technology/design tool chain from nanoscaled technology processes. The talk was illustrated by application examples of the FOSS TCAD tools, like Cogenda TCAD and DEVSIM. Compact modeling was related to the parameter extraction and standardization of the experimental and measurement data exchange formats. Finally, present FOSS CAD simulation and design tools: ngspice, Qucs, GnuCap, Xyce were presented.

~ Marcin Janicki, Editor

EDS DL MQ Gdynia Maritime University, June 20, 2018, Gdynia, Poland

EDS Distinguished Lecturer Mini-Colloquium
SiC: technology, devices, modeling
Gdynia Maritime University, June 20, 2018, Gdynia, Poland
admission: free of charge

organized by:	ED Poland Chapter Gdynia Maritime University Instytut Technologii Elektronowej (ITE, Warsaw)
technical support:	Lodz University of Technology, Department of Microelectronics and Computer Science
venue:	Gdynia Maritime University ul. Morska 83, 81-225 Gdynia, Poland

9:00-9:05

Introduction

Dr. Daniel Tomaszewski, IEEE EDS Member, ITE, Warsaw

9:05-9:50 SiC technology offerings; challenges and opportunities

Lecturer: Dr. Muhammad Nawaz, IEEE Senior Member, IEEE EDS Distinguished Lecturer,
ABB Corporate Research, Sweden

Abstract: A wide bandgap SiC technology has now entered in transitional phase on various power electronics front; thanks to its superior physical properties such as wide bandgap, larger breakdown field strength, higher carrier saturation velocity, and larger thermal conductivity than that of Si counterpart. Low voltage SiC MOSFET discrete devices and power modules within voltage range of 1.2-1.7 kV are commercially available. On the other side, medium voltage MOSFET devices of 3.3-6.5 kV and high voltage MOSFET devices of 10-15 kV are also visible in the scientific literature with excellent static and dynamic performance, illustrating the potential benefit for high power applications in energy transmission and distribution networks. This talk will focus on the requirement and issues using SiC MOSFETs facing high power applications while addressing simultaneously the potential benefits for high power converters. Reliability concerns from the end user’s perspective will be addressed as well.

10:00-10:45 On the way to the Energy and Variability Efficient (E.V.E.) Era

Lecturer: Prof. Simon Deleonibus, IEEE Fellow, IEEE EDS Distinguished Lecturer, Fellow Electrochemical Society, CEA Research Director, France

Abstract: Major power consumption reduction will drive future design of technologies and architectures that will request less greedy devices and interconnect systems. The electronic market will be able to face an exponential growth thanks to the availability and feasibility of autonomous and mobile systems necessary to societal needs. The increasing complexity of high volume fabricated systems will be possible if we aim at zero intrinsic variability, and generalize 3-dimensional integration of hybrid, heterogeneous technologies at the device, functional and system levels. Weighing on the world energy saving balance will be possible and realistic by maximizing the energy efficiency of co integrated Low Power and High Performance Logic and Memory devices.The future of Nanoelectronics will face the major concerns of being Energy and Variability Efficient (E.V.E.).

10:55-11:15 Coffee break

11:15-12:00 SiC power device fabrication and path to commercialization

Lecturer: Prof. Victor Veliadis, IEEE Fellow, IEEE EDS Distinguished Lecturer, Deputy Executive Director and CTO, PowerAmerica Professor of Electrical and Computer Engineering, North Carolina State University

Abstract: The presentation will discuss major SiC power device application areas and touch on foundry models, cost reduction strategies, and path to commercialization. The advantages of SiC over other power electronic materials will be outlined, and SiC devices currently developed for power electronic applications will be introduced. Emphasis will be placed on SiC MOSFETs, which are currently being inserted in the majority of SiC based power electronic systems. Aspects of device fabrication will be given, with stress on processes that do not carry over from the mature Si manufacturing world and are thus specific to SiC. Finally, the presentation will highlight common SiC Edge Termination techniques, which allow devices to reach their full high-voltage potential.

12:10-12:55 The importance of the diffusion currents in the photoelectric investigations of the MIS system

Lecturer: Prof. Henryk M. Przewłocki, IEEE Senior Member, IEEE EDS Distinguished Lecturer, Instytut Technologii Elektronowej (ITE Warsaw), Poland

Abstract: The fundamental property of any nanoelectronic material or system is its energy band diagram, which allows to predict its physical properties, potential applications and/or limitations. The most effective methods of band diagram determination are the photoelectric methods, which deserve therefore detailed theoretical analysis, as well as precisely controlled experimental procedures. It is shown in this paper that the commonly accepted and currently applied theory (further called classical theory) of internal photoemission in the metal-insulator-semiconductor (MIS) system, which very well represents its experimental characteristics taken at high enough electric fields E, in the insulator, fails at low electric fields (usually for E < (104-105) V/cm), i.e. in the vicinity of the point where the photocurrent changes sign (I=0). This failure of the classical theory will be demonstrated by comparing the characteristics calculated using the classical theory with the experimental characteristics taken in the range of low electric fields in the insulator. It was already shown some time ago, by the present author that this discrepancy results from the neglect of the diffusion currents, which become important at low electric fields in the insulator. In this paper the origin, the magnitude and the role of diffusion current in determination of the MIS system photoelectric characteristics at low electric fields in the insulator will be quantitatively analyzed. The theory of the photocurrent vs. gate voltage characteristics, at different wavelengths of light illuminating the structure under test, with diffusion currents taken into account will be presented. It will be shown that characteristics calculated using this theory remain in good agreement with the relevant experimental characteristics. The ability to accurately predict these characteristics in the range of low electric fields opens the possibilities of developing new measurement methods of the MIS system crucial parameters. Examples of such methods will be demonstrated.

13:05-14:05 Lunch Break

14:05-14:50 Verilog-A compact modelling of SiC devices with Qucs-S, QucsStudio and MAPP/Octave FOSS tools

Lecturer: Prof. Mike Brinson, Fellow of the IET, CEng., Member of the Institute of Physics, CPhys. Centre for Communications Technology, London Metropolitan University, UK

Abstract: The purpose of this presentation is provide an overview of the fundamentals of the Verilog-A hardware description language and its use in compact modelling of established and emerging semiconductor technology devices. With the adoption of Verilog-A as the standardised model interchange language by CMC, a knowledge of this subject is of increasing importance to the modelling community. Similarly, access to freely available Verilog-A modelling tools and circuit simulators is essential if Verilog-A modelling techniques are to be widely adopted. For this reason, in an attempt to encouraging all who attend to experiment with Verilog-A. the presentation is based on the Qucs-S, QucsStudio and the MAPP/Octave FOSS software. Throughout the talk a series of modelling case studies outline the stages in the development of Verilog-A models for established and SiC semiconductor devices. In the later stages of the presentation participants are also introduced to using the Berkeley MAPP tools with Qucs-S/Xyce.

15:00-15:45 FOSS TCAD/EDA Tools for Advanced Compact Modeling

Lecturer: Dr. Wladek Grabinski, IEEE Senior Member, IEEE EDS Distinguished Lecturer, MOS-AK (EU), Switzerland

Abstract: Compact/SPICE models of circuit elements (passive, active, MEMS, RF) are essential to enable advanced IC design using nanoscaled semiconductor technologies. Compact/SPICE models are also a communication means between the semiconductor foundries and the IC design teams to share and exchange all engineering and design information. To explore all related interactions, we are discussing selected FOSS CAD tools along complete technology/design tool chain from nanascaled technology processes; thru the MOSFET, FDSOI, FinFET and TFET compact modeling; to advanced IC transistor level design support. New technology and device development will be illustrated by application examples of the FOSS TCAD tools: Cogenda TCAD and DEVSIM. Compact modeling will be highlighted by review topics related to its parameter extraction and standardization of the experimental and measurement data exchange formats. Finally, we will present two FOSS CAD simulation and design tools: ngspice and Qucs. Application and use of these tools for advanced IC design (e.g. analog/RF IC applications) directly depends the quality of the compact models implementations in these tools as well as reliability of extracted models and generated libraries/PDKs. Discussing new model implementation into the FOSS CAD tools (Gnucap, Xyce, ngspice and Qucs as well as others) we will also address an open question of the compact/SPICE model Verilog-A standardization. We hope that this presentation will be useful to all the researchers and engineers actively involved in the developing compact/SPICE models as well as designing the integrated circuits in particular at the transistor level and then trigger further discussion on the compact/SPICE model Verilog-A standardization and development supporting FOSS CAD tools.

15:55 End of MQ

Europe-wide plastic microelectronics project

A research group of THM is operating in a Europe-wide joint project on the development of electronic circuits made of plastics. Head of the project at the THM is Prof. Dr. Alexander Klös of the competence center nanotechnology and photonics. Partners are the Spanish Universitat Rovira i Virgili, the École Polytechnique in Palaiseau France and the University of Cambridge in England.

The research projec are also participating two research institutes in France and the Netherlands and three software companies. The European Union funded the project with almost 750,000 euros to promote in particular the exchange of researchers between the participating institutions. 

Organic semiconducting materials allow the production of electronic components by conventional printing methods such as silk screen or offset printing. This alternative is far less powerful than the classic silicon technology. However, it has advantages in certain application fields and is significantly cheaper. When using chip cards or electronic labels the reduced efficiency does not matter. The market research company IDTechEx expects in 2026 a growth of the global market volume for organic electronics from currently 26.5 to 69 billion US dollars [read more...]

4th Training Course on Compact Modeling

 4th Training Course on Compact Modeling 

 (TCCM) 

 in Tarragona on June 27-28 2016

The 4th TCCM is partially sponsored by the DOMINO H2020 project. It will consist a series of lectures conducted by prestigious researchers in the field of modeling of semiconductor devices, dealing with several issues related to the semiconductor device modeling, mostly compact/SPICE modeling. It is a very interesting event to PhD students and young researchers, but can interest senior researchers too.

Invited TCCM Lecturers:

• Morgan Madec (Univ of Strasbourg, France): Compact modeling for biological applications
• Mansun Chan (Hong Kong University of Science and Technology): An Integrated Approach for Circuit Performance and Reliability Simulation
• Mohammed Nawaz (ABB Sweden): Static and dynamic characterization of SiC based MOSFETs/IGBTs
• Christoph Jungemann (RWTH-Aachen): TCAD and semiclassical device modeling
• Antonio Cerdeira (CINVESTAV, Mexico): Model parameter extraction techniques
• Fabrizio Torricelli (Univ. of Brescia, Italy): Modelling of Amorphous-Oxide-Semiconductors TFTs for large-area flexible electronics
• Eugenio Cantatore (TU-Eindhoven): Application of compact models for organic circuit design
• Ahmed Nejim (Silvaco): TCAD for compact model development
• Firas Mohammed (Infiniscale): Mathematical and Semi-physical compact modeling for emerging technologies
• Heinz Olaf Müller (Plastic Logic): Device simulation for Organic Electronics using Genius

Besides, on June 29 1016, a Workshop on Flexible Electronics will be organized, too. Attendees to TCCM who work on Flexible Electronics (not necessarily modeling) will have a chance to present recent results on their own. 

Finally, on June 30-July 1 we will organize the Annual Graduate Student Meeting on Electronic Engineering, consisting of plenary talks by prestigious researchers and student presentations. 

[more about DOMINO H2020 project at ww.domino-rise.eu]

[mos-ak] A new approach to compact semiconductor device modelling with Qucs Verilog-A analogue module synthesis

A new approach to compact semiconductor device modelling with Qucs Verilog-A analogue module synthesis  

M. E. Brinson 1,* andV. Kuznetsov 2  

Keywords:Qucs; Verilog-A analogue module synthesis;equation-defined devices (EDD); compact device modelling; circuit simulation  

Summary: Since the introduction of SPICE non-linear controlled voltage and current sources, they have become a central feature in the interactive development of behavioural device models and circuit macromodels. The current generation of SPICE-based open source general public license circuit simulators, including Qucs, Ngspice and Xyce©, implements a range of mathematical operators and functions for modelling physical phenomena and system performance. The Qucs equation-defined device is an extension of the SPICE style non-linear B type controlled source which adds dynamic charge properties to behavioural sources, allowing for example, voltage and current dependent capacitance to be easily modelled. Following, the standardization of Verilog-A, it has become a preferred hardware description language where analogue models are written in a netlist format combined with more general computer programming features for sequencing and controlling model operation. In traditional circuit simulation, the generation of a Verilog-A model from a schematic, with embedded non-linear behavioural sources, is not automatic but is normally undertaken manually. This paper introduces a new approach to the generation of Verilog-A compact device models from Qucs circuit schematics using a purpose built analogue module synthesizer. To illustrate the properties and use of the Qucs Verilog-A module synthesiser, the text includes a number of semiconductor device modelling examples and in some cases compares their simulation performance with conventional behavioural device models. Copyright © 2016 John Wiley & Sons, Ltd.  

Article first published online: 15 APR 2016; DOI: 10.1002/jnm.2166  

References
[1] Newton AR, Pederson DO, Sangiovanni-Vincentelli A. SPICE Version 2g User's Guide. Department of Electrical Engineering and Computer Sciences, University of California: Berkeley, CA, 1981.
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[2] Johnson B, Quarles T, Newton AR, Pederson DO, Sangiovanni-Vincentelli A. Berkeley, CA. Department of Electrical Engineering and Computer Sciences, University of California, 1992.
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[3] Brinson M, Crozier R, Kuznetsov V, Novak C, Roucaries B, Schreuder F, Torri GT. Qucs (Quite universal circuit simulator), 2015. Available from: http;//qucs.sourceforge.net [Accessed November 2015].
[4] Nenzi P, Vogt H. Ngspice-26 (Next generation SPICE version 26), 2015. Available from: http://ngspice.sourceforge. net. [Accessed November 2015].
[5] Sandia National Laboratories, US, Xyce parallel electronic simulator version 6.3., 2015. Available from: http: //xyce.sandia.gov.[Accessed November 2015].
[6] Jahn S, Brinson ME. Interactive compact device modelling using Qucs equation-defined devices. International Journal of Numerical Modelling: Electronic Networks, Devices and Fields 2008; 21(5): 335–349.
Direct Link:
Abstract PDF(1011K) References Web of Science® Times Cited: 7 Go here for SFX
[7] Brinson ME, Jahn S. Qucs: a GPL software package for circuit simulation, compact device modelling and circuit macromodelling from DC to RF and beyond. International Journal of Numerical Modelling: Electronic Networks, Devices and Fields 2009; 22(4): 297–319.
Direct Link:
Abstract PDF(1156K) References Web of Science® Times Cited: 7 Go here for SFX
[8] Accellera, Verilog-AMS Language Reference Manual. Version 2.3.1., 2009. Available from: http://www.accellera.org. [Accessed November 2015.]
[9] Silicon Integration Initiative (Si2), Compact Model Coalition, 2015. Available from: http;//www.si2.org. [Accessed November 2015.]
[10] Brinson ME, Jahn S. Modelling high-frequency inductance with Qucs non-linear radio frequency equation defined devices.International Journal of Electronics 2009; 96(3): 307–321.
CrossRef, Web of Science® Times Cited: 1
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[11] Lemaitre L, Gu B. ADMS - A fully Customizable Compact Model Compiler, NSTI-Nanotech, 2008. Available from: www.nsti.org[Accessed March 2016].
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[12] Lemaitre L, Grabinski W, McAndrew C. Compact device modelling using Verilog-AMS and AMS. Electron Technology (Internet Journal). June 6 2003, pp 1-5. Available from: http://www.ite.waw.pl/etij/pdf/35-03p.pdf. [Accessed November 2015.]
[13] Lemaitre L, McAndrew CM, Hamm S. Automatic Device Model Synthesis. CICC: Florida, USA, 2002.
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[14] Eaton JW. GNU Octave. Version 4.0, 2015. Available from: https:www.gnu.org/software/octave/. [Accessed November 2015.]
[15] Brinson M, Crozier R, Novak C, Roucaries B, Schreuder F, Torri GT. Building a second generation Qucs GPL circuit simulator: package structure, simulation features and compact device modelling capabilities. London, 2014. Available from: http://www.mos-ak.org/london−2014/presentations/09−Mike−Brinson−MOS-AK−London−2014.pdf. [Accessed November 2015].
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[16] Brinson M, Crozier R, Kuznetsov V, Novak C, Roucaries B, Schreuder F, Torri GT. Qucs: an introduction to the new simulation and compact device modelling features implemented in release 0.0.19/0.0.19Src2 of the popular GPL circuit simulator. MOS-AK ESSDERC/ESSCIRC Workshop. 18 September Graz, Austria 2015. Available from: http://www.mos-ak.org/graz−2015/presentationsT−5−Brinson−MOS-AK−Graz−2015.pdf. [Accessed November 2015].
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[17] Anognetti P, Massobrio G. Semiconductor Device Modeling with SPICE. McGraw-Hill Inc: New York, 1988.
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