[mos-ak] [2nd Announcement and C4P] 4th International MOS-AK/LAEDC Workshop July 3 Puebla (MX)

2nd Announcement and C4P

Together with local online host, the LAEDC Organizers as well as all the Extended MOS-AK TPC Committee, would like to invite you to the 4th International MOS-AK/LAEDC Workshop which will be organized as the virtual/online event on July 3  between 8:30am -  12:30pm (UTC/GMT -5 hours) as a hybrid event in Puebla (MX) providing an opportunity to meet with modeling engineers and researchers from Europe and Latin America.

Upcoming MOS-AK/LAEDC Workshop aims to strengthen a network and discussion forum among experts in the field, enhance an open platform for information exchange related to compact/SPICE modeling and Verilog-A standardization, bring academic and industrial experts in the compact modeling field together, as well as obtain feedback from technology developers, circuit designers, and CAD/EDA tool developers and vendors, in particular using Free 130nm Skywater PDK.

Topics to be covered include the following among other related to the compact/SPICE modeling and its Verilog-A standardization:

• Compact Modeling (CM) of the electron devices
• Advances in semiconductor technologies and processing
• Verilog-A language for CM standardization
• New CM techniques and extraction software
• Open Source (FOSS) TCAD/EDA modeling and simulation
• CM of passive, active, sensors and actuators
• Emerging Devices, Organic TFT, CMOS and SOI-based memory
• Microwave, RF device modeling, high voltage device modeling
• Nanoscale CMOS, BiCMOS, SiGe, GaN, InP devices and circuits
• Technology R&D, DFY, DFT and reliability/aging IC designs
• Foundry/Fabless Interface Strategies (eg: Skywater 130nm CMOS)

List of MOS-AK speakers (tentative in alphabetical order) :

• Sergio Bampi, UFRGS (BR)
• Juan Brito, IMPINJ (BR)
• Antonio Cerdeira, CINVESTAV (MX)
• Benjamin Iniguez, URV (SP)
• Roberto Murphy, INAOE (MX)
• Jean-Michel Sallese, EPFL (CH)
• Gilson I Wirth, UFRGS (BR)

Online Abstract Submission is open (any related enquiries can be sent to abstracts@mos-ak.org)

Online Event Registration is open (any related enquiries can be sent to registration@mos-ak.org)

Important Dates: 

• Call for Papers: Dec. 2021
• 2nd Announcement: May 2022
• Final Workshop Program: June 2022
• MOS-AK: July 3 2022, Puebla (MX)
• 8:30am - 12:30pm (UTC/GMT -5 hours) MOS-AK Workshop

W.Grabinski for Extended MOS-AK Committee

WG170522

[paper] Compact Schottky-barrier CNTFET Modeling

Manojkumar Annamalai and Michael Schroter

Compact formulation for the bias dependent quasi-static mobile charge in Schottky-barrier CNTFETs IEEE Transactions on Nanotechnology (2021)

DOI: 10.1109/TNANO.2021.3116694

CEDIC, Technische Universität Dresden (D)

Abstract: Carbon nanotube (CNT) field-effect transistors (FETs) are promising candidates for future high-frequency (HF) system-on-chip applications. Understanding and modeling mobile charge storage on CNTs is therefore essential for device optimization and circuit design. A physics-based compact analytical formulation is presented that enables an accurate approximation of the mobile charge in Schottky-barrier CNTFETs over the practically relevant bias range for HF circuit design. The formulation is C∞ continuous and yields accurate results also for the capacitances. The new formulation has been verified for both ballistic and scattering dominated carrier transport by employing device simulation, which was calibrated to experimental data from multi-tube CNTFETs.

Fig: Band diagram in a CNTFET along the axial direction (left red arrow) and, with applied gate bias, along the radial direction perpendicular to the gate (right blue arrow).

Acknowledgments: The authors would like to thank Dr. S. Mothes, formerly with CEDIC, for valuable discussions regarding the device simulator. This project was financially supported in part by the German National Science Foundation (DFG SCHR695/6-2).  

[paper] MOSFET Threshold Voltage Extraction

Nikolaos Makris and Matthias Bucher (IEEE Member)

On MOSFET Threshold Voltage Extraction 

Over the Full Range of Drain Voltage Based on Gm/ID

arXiv:2106.00747v1 [physics.app-ph] 1 June 2021

Abstract: A MOSFET threshold voltage extraction method covering the entire range of drain-to-source voltage, from linear to saturation modes, is presented. Transconductance-to-current ratio is obtained from MOSFET transfer characteristics measured at low to high drain voltage. Based on the charge-based modeling approach, a near-constant value of threshold voltage is obtained over the whole range of drain voltage for ideal, long-channel MOSFETs. The method reveals a distinct increase of threshold voltage versus drain voltage for halo-implanted MOSFETs in the low drain voltage range. The method benefits from moderate inversion operation, where high-field effects, such as vertical field mobility reduction and series resistances, are minimal. The present method is applicable over the full range of drain voltage, is fully analytical, easy to be implemented, and provides more consistent results when compared to existing methods.

Fig: Extraction of threshold voltage for a long-channel MOSFET from transconductance-to-current ratio (TCR) covering linear to saturation modes. (a) GmUT /ID obtained from ID vs. VG characteristics measured at different values of VDS (long-channel n-MOSFET) together with model (b) Criterion for threshold voltage nGmUT /ID varies among two asymptotic values in linear and saturation modes.

Aknowlegements: This work was partly supported under Project INNOVATION-EL-Crete (MIS 5002772).

Related papers:

[i] T. Rudenko, V. Kilchytska, M. K. M. Arshad, J. Raskin, A. Nazarov and D. Flandre, "On the MOSFET Threshold Voltage Extraction by Transconductance and Transconductance-to-Current Ratio Change Methods: Part I—Effect of Gate-Voltage-Dependent Mobility," in IEEE Transactions on Electron Devices, vol. 58, no. 12, pp. 4172-4179, Dec. 2011.

doi: 10.1109/TED.2011.2168226

[ii] T. Rudenko, V. Kilchytska, M. K. M. Arshad, J. Raskin, A. Nazarov and D. Flandre, "On the MOSFET Threshold Voltage Extraction by Transconductance and Transconductance-to-Current Ratio Change Methods: Part II—Effect of Drain Voltage," in IEEE Transactions on Electron Devices, vol. 58, no. 12, pp. 4180-4188, Dec. 2011.

doi: 10.1109/TED.2011.2168227

[iii] T. Rudenko, V. Kilchytska, M. K. M. Arshad, J. Raskin, A. Nazarov and D. Flandre, "Influence of drain voltage on MOSFET threshold voltage determination by transconductance change and gm/Id methods," ULIS, Cork, Ireland, 2011, pp.1-4.

doi: 10.1109/ULIS.2011.5758012

[paper] JART VCM v1 Verilog-A Compact

JART VCM v1 Verilog-A Compact

Model User Guide

Christopher Bengel, David Kaihua Zhang, Rainer Waser, Stephan Menzel

Electronic Materials Research Laboratory; RWTH Aachen University
Forschungszentrum Jülich

Abstract: The JART VCM v1a model was developed to simulate the switching characteristics of ReRAM devices based on the valence change mechanism. In this model, the ionic defect concentration (oxygen vacancies) in the disc region close to the active electrode (AE) defines the resistance state. The concentration changes due to the drift of the ionic defects. Furthermore, these oxygen vacancies act as mobile donors and modulate the Schottky barrier at the AE/oxide interface. In this model, Joule heating is considered, which significantly accelerates the switching process at high current levels. Since the JART VCM v1b model represents an improvement of the JART VCM v1a model, this user guide will have its focus on the JART VCM v1b model. Here, the equivalent circuit diagram (ECD) as well as some equations have been modified to explain the switching dynamics more accurately  Based on the JART VCM v1b model, a variability model was developed, which includes both device-to-device and cycle-to-cycle variability. In terms of the device-to-device variability, the VCM cells are initiated with statistical distributed parameters: filament lengths, filament radii and maximum and minimum values for the oxygen vacancy concentration in the disc. The cycle-to-cycle variability is achieved by changing the four quantities during SET and RESET. The latest extension of the JART VCM v1b also includes RTN, which is based on statistical jumps of oxygen vacancies into and out of the disc region.

Fig: Equivalent circuit diagram of the JART VCM v1b model (a) 

along with the electrical model in Verilog-A (b).

The Verilog-A code of this model can be downloaded here (Verilog-A file).
The User Guide for this model version can be downloaded here (User Guide PDF).

[paper] Compact Modeling as a Bridge between Technologies and ICs

Compact Modeling as a Bridge 

between Scaled Semiconductor Technologies and Advanced Designs of the Integrated Circuits

AB Bhattacharyya and Wladek Grabinski

IETE Journal of Research 58(3):179-180 (May 2012)

DOI: 10.4103/0377-2063.97322

Abstract: The quality of the integrated circuits analysis, required in present contemporary design flows, is directly linked to the accuracy of its basic components—the Compact Model/Simulation Program with Integrated Circuit Emphasis (SPICE) Model. The compact/SPICE modeling is an essential research activity bridging scaled semiconductor technologies and advanced designs of the integrated circuits. To enable complete access to the new advanced semiconductor technologies, the designers have to frequently update their Computer-Aided Design (CAD) tools with accurate definition of the semiconductor device models that can be implemented into the CAD circuit simulators. The models must preferably be physics-based to account for complex dependencies of the device properties and defined in standard, high-level language, i.e., Verilog-A, to simplify access and implementation into the CAD tools. For the state of the art advanced CMOS technologies (analog, HV, SOI), both modeling and characterization are challenging tasks that will be emphasized in this special issue of Compact Modeling. (REF) Compact Modeling as a Bridge between Scaled Semiconductor Technologies and Advanced Designs of the Integrated Circuits. 

Available from: <http://www.mos-ak.org/india/>

and https://www.researchgate.net/publication/278384752_Compact_Modeling_as_a_Bridge_between_Scaled_Semiconductor_Technologies_and_Advanced_Designs_of_the_Integrated_Circuits

[paper] SPICE Compact Model for Schottky-Barrier FETs

Sheikh Aamir Ahsan, Member, IEEE, Shivendra Kumar Singh, Chandan Yadav, Member, IEEE, Enrique G. Marín, Member, IEEE, Alexander Kloes, Senior Member, IEEE

and Mike Schwarz, Senior Member, IEEE

A Comprehensive Physics-Based Current–Voltage SPICE Compact Model 

for 2-D-Material-Based Top-Contact Bottom-Gated Schottky-Barrier FETs

IEEE Transactions on Electron Devices, vol. 67, no. 11, pp. 5188-5195, Nov. 2020

DOI: 10.1109/TED.2020.3020900

Abstract: In this article, we report the development of a novel physics-based analytical model for explaining the current–voltage relationship in Schottky barrier (SB) 2D material field effect transistors (FETs). The model has at its core the calculation of the surface-potential (SP) which is accomplished by invoking 2-D density of states in conjunction with Fermi–Dirac (FD) distribution for electron and hole statistics. The explicit computation for the SP, carried out using the Lambert-W function together with Halley’s method, is used to construct the SP-based band-diagram for realizing the transparency of the SBs. Thereafter, the ambipolar current is derived in terms of the electron and hole injection phenomena the thermionic emission and Fowler–Nordheim tunneling mechanisms at the SB contacts. Furthermore, drift-diffusion current is derived in terms of the SP and incorporated in the model to account for the scattering in the intrinsic 2D channel. Finally, the Verilog-A model is validated against experimental IV data reported in the literature for two different 2D material systems. This is the first demonstration of an explicit SP-based SPICE model for ambipolar SB-2-D-FETs that is simultaneously built on tunneling-emission and driftdiffusion formalisms.

Fig: (a) Band-diagram sketched along positive y-direction underneath the source electrode. Blue and black lines represent bands before and after applying Vgs. (b) ψ-based diagram sketched along positive x, constructed after calculating ψs and ψd. The geometrical screening length λ is given by λ ≈ (tox t2D)^1/2.

Acknowledgement: This work was supported in part by the National Project Implementation Unit (NPIU) through the third phase of Technical Education Quality Improvement Programme (TEQIP-III) Project and in part by DST-SERB Startup Research Grant under Award SRG/2019/001122.