[paper] 20 Years of Reconfigurable Field-Effect Transistors

T. Mikolajick^1,2, G. Galderisi¹, M. Simon¹, S. Rai³, A. Heinzig², A. Kumar³, 

W.M. Weber⁴, J. Trommer¹

20 Years of Reconfigurable Field-Effect Transistors: From Concepts to Future Applications 

22th Conference on Insulating Films on Semiconductors 

INFOS2021

28 June-2 July 2021, Rende, Italy

1 NaMLab GmbH, Nöthnitzer Str. 64a, Dresden, Germany
2 Chair of Nanoelectronics, TU Dresden, Germany
3 Chair of Processor Design, TU Dresden, Dresden, Germany
4 Chair of Nanoelectronics, TU Wien, Vienna, Austria

Outline

• Introduction
• The Reconfigurable Field Effect Transistor
• Early Phase
• Device Outgrowth
• Functional Diversification
• Summary and Outlook

[paper] Compact Modeling of Carbon Nanotube FETs

A Compact and Robust Technique for the Modeling and Parameter Extraction 

of Carbon Nanotube Field Effect Transistors

Laura Falaschetti¹, Davide Mencarelli¹, Nicola Pelagalli¹, Paolo Crippa¹, Giorgio Biagetti¹,

Claudio Turchetti¹,George Deligeorgis², and Luca Pierantoni¹

Electronics 2020, 9(12), 2199; 

DOI: 10.3390/electronics9122199

1 Department of Information Engineering, Marche Polytechnic University, 60131 Ancona, Italy
2 Microelectronics Research Group (MRG/IESL), FORTH, Greece

Abstract: Carbon nanotubes field-effect transistors (CNTFETs) have been recently studied with great interest due to the intriguing properties of the material that, in turn, lead to remarkable properties of the charge transport of the device channel. Downstream of the full-wave simulations, the construction of equivalent device models becomes the basic step for the advanced design of high-performance CNTFET-based nanoelectronics circuits and systems. In this contribution, we introduce a strategy for deriving a compact model for a CNTFET that is based on the full-wave simulation of the 3D geometry by using the finite element method, followed by the derivation of a compact circuit model and extraction of equivalent parameters. We show examples of CNTFET simulations and extract from them the fitting parameters of the model. The aim is to achieve a fully functional description in Verilog-A language and create a model library for the SPICE-like simulator environment, in order to be used by IC designers.

Figure 2. 3D structure of CNTFET. Reprinted, with permission, from [I and II]

Aknowlwgement: This research was supported by the European Project “NANO components for electronic SMART wireless circuits and systems (NANOSMART)”, H2020—ICT-07-2018-RIA, n. 825430.

References:

[I] Deng, J.; Wong, H.P. A Compact SPICE Model for Carbon-Nanotube Field-Effect Transistors Including non-idealities and Its Application—Part I: Model of the Intrinsic Channel Region. IEEE Trans. Electron Devices 2007, 54, 3186–3194

[II] Deng, J.; Wong, H.P. A Compact SPICE Model for Carbon-Nanotube Field-Effect Transistors Including non-idealities and Its Application—Part II: Full Device Model and Circuit Performance Benchmarking. IEEE Trans. Electron Devices 2007, 54, 3195–3205 

[paper] Compact Model for Ferroelectric FET

Lu, Darsen, Sourav De, Mohammad Aftab Baig, Bo-Han Qiu, and Yao-Jen Lee

Computationally efficient compact model for ferroelectric field-effect transistors 

to simulate the online training of neural networks

Semiconductor Science and Technology (2020)

DOI: 10.1088/1361-6641/ab9bed

Abstract: In this paper, a compact drain current formulation that is simple and adequately computationally efficient for the simulation of neural network online training was developed for the ferroelectric memory transistor. Tri-gate ferroelectric field effect transistors (FETs) with Hf0.5Zr0.5O2 gate insulators were fabricated with a gate-first high-k metal gate CMOS process. Ferroelectric switching was confirmed with double sweep and pulse programming and erasure measurements. Novel characterization scheme for drain current was proposed with minimal alteration of ferroelectric state in subthreshold for accurate threshold voltage measurements. The resultant threshold voltage exhibited highly linear and symmetric across multilevel states. The proposed compact formulation accurately captured the FET gate-bias dependence by considering the effects of series resistance, Coulomb scattering, and vertical field dependent mobility degradation.

Fig.: Transmission electron micrograph of the fabricated tri-gate Fe

finFET device across the fin, with approximately 60 nm fin width, 30 nm fin

height, and 10 nm HZO Fe layer.

Acknowledgements: This work was jointly supported by the Ministry of Science and Technology (Taiwan) grant MOST–108–2634–F–006–08 and is part of research work by MOST’s AI Biomedical Research Center. We are grateful to the Taiwan Semiconductor Research Institute for nanofabrication facilities and services and to Dr. Wen-Jay Lee and Nan-Yow Chen of the National Center for High-Performance Computing for helpful suggestions on AI computation. This manuscript was edited by Wallace Academic Editing.