[paper] Above Vth Model for SC DG MOSFETs

David Chuyang Hong; Yuan Taur

An Above Threshold Model for Short-Channel DG MOSFETs

in IEEE TED, vol. 68, no. 8, pp. 3734-3739, Aug. 2021

DOI: 10.1109/TED.2021.3092310.

*Department of Electrical and Computer Engineering, University of California at San Diego, La Jolla, CA 92093 USA

Abstract: An above-threshold I–V model is developed for short-channel double-gate (DG) MOSFETs. It is a non-gradual channel approximation (non-GCA) model that takes into account the contribution to carrier density from the encroachment of source–drain bands into the channel. At low-drain bias voltages, the effect appears as a gate-voltage-dependent reduction of channel resistance, with stronger effects at low gate overdrives. At high-drain biases, the intersection of source band encroachment with the gate-controlled channel potential leads to a point of virtual cathode a small distance from the source. By incorporating the depletion of carriers in the source and drain regions into the boundary conditions, the Ids-Vds and Ids-Vgs characteristics generated by the model are shown to be consistent with TCAD simulations.

Figure below shows the schematic of a DG MOSFET (undoped). The device operation is governed by 2-D Poisson’s equation

Fig: Schematic of a DG MOSFET. The parameters assumed are tsi=4nm, ti=2nm, εsi=εi=11.8ε0, with channel length L ranging from 15 to 7nm. The gate work function is 0.28eV below that of intrinsic silicon so Vt=0.247V.

[paper] Electrostatically doped drain engineered DG‐TFET

Shaikh, MRU, Loan, SA, Alshahrani, A.
Electrostatically doped drain engineered DG‐TFET:
Proposal and Analysis
IJNM 2020;e2769
DOI: 10.1002/jnm.2769

Abstract: In this paper, a drain‐engineered double‐gate Tunnel‐FET (DE‐DG‐TFET) to enhance the electrical characteristics and analog parameters of a conventional DG‐TFET is proposed and examined through calibrated TCAD simulations. Unlike DG‐TFET, a constant n‐type doping, N_cd, (5E17 cm⁻³ − 2E18 cm⁻³), in the channel/drain regions of DE‐DG‐TFET is used, resulting in a p+‐n‐n structure instead of conventional p+‐i‐n structure. Further, p+‐n‐n is modified to p+‐n‐n+ using electrostatic doping (ED) method on the drain side with Hafnium (ϕ_m = 3.9 eV) as a lateral (top and bottom) and side metal electrode. A high n+‐drain doping ensures the drain contact remains ohmic. Higher electric field at p+‐n source‐channel junction enhances the ON‐state BTBT current. While the absence of metallurgical junction provides large tunneling width across the channel/drain junction, resulting in suppression of ambipolar current (I_AMB). At N_cd doping of 1E18 cm⁻³, DE‐DG‐TFET demonstrates ~7 times increase in I_ON while I_AMB is suppressed by ~5 orders of magnitude. In addition to this, the proposed device improves analog/RF figures of merit, 45% in voltage gain and ~5 times in peak f_T.

FIG: Key steps for fabrication of the proposed DEDG-TFET

Acknowledgement: This work was supported by Ministry of Electronics & Information Technology (MeitY), Government of India through Visvesvaraya PhD Scheme.