Showing posts with label ESSCIRC. Show all posts
Showing posts with label ESSCIRC. Show all posts

Dec 18, 2023

[C4P] 50th ESSERC, Sept. 9-12. 2024, Bruges (BE)

CALL FOR PAPERS
https://www.esserc2024.org/papers

The aim of ESSERC (European Solid-State Electronics Conference) is to provide an annual European forum for the presentation and discussion of recent advances in solid-state devices and circuits. It is a continuation of the past ESSDERC-ESSCIRC conferences. The level of integration for system-on-chip design is rapidly increasing. This is made available by advances in semiconductor technology. Therefore, more than ever before, a deeper interaction among technologists, device experts, IC designers and system designers is necessary. 
ESSERC is governed by a Steering Committee and consists of Plenary Keynote Presentations, invited papers and session on technology, circuits and joint papers bridging both device and circuit communities, respectively. 

PAPERS SUBMISSION DEADLINE: APRIL 5, 2024

Papers submitted for review must clearly state:
  • The purpose of the work
  • How and to what extent it advances the state-of-the art
  • Specific results and their impact
Only work that has not been previously published or submitted elsewhere will be considered. Submission of a paper for review and subsequent acceptance is considered as a commitment that the work will not be publicly available prior to the conference. Measurement results or calibration against measured data is required to support the claims of the submitted paper.

After selection of papers, the authors will be informed about the decision of the Technical Program Committee by e-mail by 24 May 2024.

At the same time, the complete program will be published on the conference website. An oral presentation will be given at the Conference for each accepted paper. No-shows will result in the exclusion of the papers from any conference related publication. The submitted final PDF files should be IEEE Xplore compliant.

For each paper independently, at least one (co-)author is required to register for the Conference (one registration one paper policy). Registration fees and deadlines will be soon available

CONFERENCE TRACKS (although not limited, papers are solicited for the following main topics):
  1. Advanced Technology, Process and Materials
  2. Analog, Power and RF Devices
  3. Compact Modeling and Process/Device Simulation
    TCAD and advanced simulation techniques and studies, compact/ SPICE modeling of electronic, optical, organic, emerging, and hybrid devices and their IC implementation and interconnection. Verilog-A models of semiconductor devices (including bio/ med sensors, MEMS, microwave, RF, high voltage and power, emerging technologies, and novel devices), parameter extraction, reliability and variability, performance evaluation and open-source benchmarking/implementation methodologies. Modeling of interactions between process, device and circuit design, design/technology co-optimization, foundry/fabless interface strategies. Numerical, analytical, statistical modeling and simulation of electronic, optical and hybrid devices, interconnect, isolation, and 2D/3D integration. Simulations of material properties and fabrication processes. Advanced physical phenomena (quantum mechanical and non-stationary transport phenomena, ballistic transport). Mechanical and/or electro-thermal modeling and simulation. Simulations of reliability aspects of materials and devices.
  4. Analog Circuits
  5. Data Converters
  6. RF & mm-Wave Circuits
  7. Frequency Generation Circuits
  8. Digital Circuits & Systems
  9. Power Management
  10. Wireless Systems
  11. Wireline and Optical Circuits and Systems
  12. Emerging Computing Devices and Circuits
  13. Architectures and Circuits for AI and ML
  14. Devices & Circuits for Sensors, Imagers and Displays
WHY BRUGES?
Bruges is a place that lives and breathes history. Visiting this historic city means travelling back in time to the Middle Ages. It is both magical and authentic. Brugge in medieval times was known as a commercial metropolis in the heart of Europe. 
Bruges is one of Europe’s best-preserved cities, evidenced by the fact that its historic city center has been designated an UNESCO World Heritage Site. The iconic spires of its cathedral and bell tower, its cobbled streets, winding canals and whitewashed façades are almost painfully picturesque.
In the 15th century, Brugge was the cradle of the Flemish Primitives and a center of patronage and painting development for artists such as Jan van Eyck and Hans Memling. Many of their works were exported and influenced painting styles all over Europe. Exceptionally important collections have remained in the city until today. Travelers from all over the world are coming to Belgium to visit Bruges.

Nov 24, 2021

ESSCIRC/ESSDERC 2021 The Best Paper Awards

The #ESSCIRC #ESSDERC TPC is proud to announce The Best Paper Awards from ESSCIRC/ESSDERC 2021 in Grenoble, selected by our Technical Program Committee members:
  • BEST JOINT PAPER 2021: “Low Power Indirect Time-of-Flight Pixel Achieving 88.5% Demodulation Contrast at 200MHz for 0.54MPix Depth Camera” by Cedric Tubert et al., STM (F)
  • BEST STUDENT JOINT PAPER 2021: “Cryogenic Characterization and Modeling of 14 nm Bulk FinFET Technology”, by @Asma Chabane, IBM Research GmbH
  • BEST ESSDERC PAPER 2021: “Complementary Two-Dimensional (2-D) MoS_2 FET Technology”, by @Cristine Jin Estrada et al., The Hong Kong UST
  • BEST ESSDERC STUDENT PAPER 2021:“VERILOR: a Verilog-a Model of Lorentzian Spectra for Simulating Trap-Related Noise in CMOS Circuits”, by @Angeliki Tataridou, IMEP-LaHC, Université Grenoble Alpes, University Savoie Mont Blanc, CNRS, Grenoble INP
  • BEST ESSCIRC PAPER 2021: “A Resolution-Adaptive 8mm2 9.98Gb/S 39.7pJ/B 32-Antenna All-Digital Spatial Equalizer for mmWave Massive MU-MIMO in 65nm CMOS”, by @Oscar Castaneda et al., ETH Zürich and Cornell Univ.
  • BEST ESSCIRC STUDENT PAPER 2021:”A −109.1 dB/−98 dB THD/THD+N Chopper Class-D Amplifier with >83.7 dB PSRR Over the Entire Audio Band”, by @Huajun Zhang et al., TU Delft
Warm congratulations to all the authors, and see you in Milano, September 19-22, 2022 at #ESSCIRC-#ESSDERC Conference for the Award Ceremony!

Sylvain CLERC Francois Andrieu Louis Hutin 
on the behalf off#ESSCIRC #ESSDERC TPC








Jul 21, 2021

[Final Program] 18th MOS-AK ESSDERC/ESSCIRC Workshop Grenoble; Sept. 6, 2021

MOS-AK ESSDERC/ESSCIRC Workshop Grenoble
Arbeitskreis Modellierung von Systemen und Parameterextraktion
Modeling of Systems and Parameter Extraction Working Group
18th MOS-AK ESSDERC/ESSCIRC Workshop
Grenoble, Sept. 6, 2021

Together with local Host and MOS-AK Organizers as well as all the Extended MOS-AK TPC Committee, we invite you to the consecutive 18th MOS-AK ESSDERC/ESSCIRC Workshop. Scheduled Virtual/Online MOS-AK event aims to strengthen a network and discussion forum among experts in the field, enhance open platform for information exchange related to compact/SPICE modeling and Verilog-A standardization, bring people in the compact modeling field together, as well as obtain feedback from technology developers, circuit designers, and TCAD/EDA tool developers and vendors.

The MOS-AK Workshop Program is available online: 

Venue: Online MOS-AK Webinar;
use the online form/link below to register.

Online Registration is open
any related enquiries can be sent to registration@mos-ak.org

Post-workshop publications, selected, the best papers will be recommended for further publication in the special compact/SPICE modeling issue of the Solid State Electronics.

-- W.Grabinski; MOS-AK (EU)

Enabling Compact Modeling R&D Exchange

WG210721

Jun 9, 2020

Virtual Education Events at ESSDERC/ESSCIRC 2020


Given this uncertain situation, the organizing committee of ESSDERC/ESSCIRC 2020 in Grenoble and its Steering Committee, have decided to propose a new format for coming conference, which will include a NEW and Virtual Education Event series being developed for September 14th 2020 consisting of 13 educational sessions (workshops and tutorial) comprising invited presentations by leading academic and industrial experts and technologists. All related technical program details are also available online: https://www.esscirc-essderc2020.org/educationals

1. TUTORIAL | Quantum Computing: Myth or Reality?
Chairs: M. Vinet (CEA) and Farhana Sheikh (Intel)
Full content duration ~6h
2. WORKSHOP | Emerging Solutions for Imaging Devices, Circuits and Systems
Chairs: Matteo Perenzoni (FBK) and Albert Theuwissen (Harvest Imaging)
Full content duration ~6h
3. WORKSHOP | Non-Volatile Memories: Opportunities and Challenges from Devices to Systems
Chairs: Gabriel Molas (CEA) and Mahmut Sinangil (TSMC)
Full content duration ~6h
4. WORKSHOP | New 5G integration solutions, and related technologies (from materials to system)
Chairs: Nadine Collaert (imec) and Stefan G. Andersson (Ericsson)
Full content duration ~6h
5. WORKSHOP | Advances in device technologies for automotive industry (power devices, SiC, GaN)
Chairs: Ionut Radu (Soitec) and Stefaan Decoutere (IMEC)
Full content duration ~6h
6. WORKSHOP | Embedded monitoring and compensation design for energy or safety constrained applications
Chairs: Sylvain Clerc (ST) and Keith Bowman (Qualcomm)
Full content duration ~4h
7. WORKSHOP | Edge AI and In-Memory-Computing for energy efficient AIoT solutions​
Chairs:  Andreas Burg (EPFL) and Marian Verhelst (KUL)
Full content duration ~6h
8. WORKSHOP | Ab-initio simulations supporting new materials & process developments
Chairs: Denis Rideau (ST) and Philippe Blaise (Silvaco)
Full content duration ~3h
9. WORKSHOP | RISC-V cooking session
Chairs: Bora Nikolic (BWRC)
Full content duration ~3h
10. DISSEMINATION WORKSHOP |  Toward sustainable IOT from rare materials to big data
Chairs:  Thierry Baron (CEA, LTM/UGA) and Audrey Dieudonné (UGA)
Full content duration ~3h
11. DISSEMINATION WORKSHOP | High Density 3D CMOS Mixed-Signal Opportunities
Chair: Philipp Häfliger (UiO)
Full content duration ~3h
12. MOS-AK WORKSHOP | Compact/SPICE Modeling and its Verilog-A Standardization
Chair: Wladek Grabinski (MOS-AK) and Daniel Tomaszewski (ITE Warsaw)
Full content duration ~6h
13. IPCEI on Microelectronics: Innovative Technologies for Shaping the Future
Chairs: Dominique Thomas (ST), Klaus Pressel (Infineon), Rainer Pforr (Zeiss)
Full content duration ~6h

Apr 1, 2020

[C4P] ESSDERC TRACK3 Compact Modeling


European ESSDERC/ESSCIRC conference will be organized in Grenoble (F) on Sept.14-18, 2020 with its integral TRACK3: Compact Modeling and Process/Device Simulation which is open for submissions, now. You and all your R&D partners are welcome to submit a modeling paper. The paper submission deadline is April 17, 2020

TRACK3: Compact modeling and process/device simulation (including TCAD and advanced simulation techniques and studies)  focuses on following domains among other R&D topics:
  • Compact/SPICE modeling of electronic, optical, organic, and hybrid devices and their IC implementation and interconnection. 
  • Verilog-A models of the semiconductor devices (including Bio/Med sensors, MEMS, Microwave, RF, HV and Power, emerging technologies and novel devices)
  • Compact/SPICE parameter extraction
  • Performance evaluation and open source (FOSS) benchmarking/implementation methodologies
  • Modeling of interactions between process, device and circuit design, 
  • Foundry/Fabless interface strategies
  • Numerical TCAD, analytical, statistical modeling and simulation of electronic, optical and hybrid devices, interconnect, isolation and 2D/3D integration
  • Aspects of materials, fabrication processes and devices e.g. advanced physical phenomena (quantum mechanical and non-stationary transport phenomena, ballistic transport, ...)
  • Optical, mechanical or electro-thermal modeling and simulation
  • DfM, ageing, reliability of materials and devices
Please share our TRACK3 C4P with all your academic and industrial R&D partners active in the compact/SPICE modeling, Verilog-A standardization and TCAD/EDA simulations. Of course, your and your research team proactive contribution to our TRACK3 is more than welcome. I do hope that despite of a last minute notice, with your help, we will be able to draw even more attention to the ESSDERC/ESSCIRC Conference and, in particular, our modeling TRACK3



Dec 2, 2019

[C4P] 50th ESSDERC / 46th ESSCIRC

Grenoble (F) Sept.14-18 2020
Call for Papers

The aim of ESSCIRC and ESSDERC is to provide an annual European forum for the presentation and discussion of recent advances in solid-state devices and circuits. The level of integration for system-on-chip design is rapidly increasing. Therefore, more than ever before, a deeper interaction among technologists, device experts, IC designers and system designers is necessary. While keeping separate Technical Program Committees, ESSDERC and ESSCIRC are governed by a common Steering Committee and share Plenary Keynote Presentations and Joint Sessions bridging both communities. Attendees registered for either conference are encouraged to attend any of the scheduled parallel sessions, regardless to which conference they belong.

TPC Tracks:

  • Advanced Technology, Process and Materials
  • Analog, Power and RF Devices
  • Compact modeling and process/device simulation
  • Joint TRACK: Memory devices and circuits towards non Von Neumann
  • Joint TRACK: Emerging Computing Devices and Circuits
  • Joint TRACK: Devices and circuits for Sensors, Optoelectronics and Display
  • Analog Circuits
  • Data Converters Circuits
  • RF & mmW Circuits
  • Frequency Generation Circuits
  • Wireless & Wireline Circuits & Systems
  • Digital Circuits & Systems
  • Power Management Circuits

Dec 19, 2016

[Call for Papers] ESSCIRC–ESSDERC 2017



September 11-14, 2017
LEUVEN - Belgium
www.esscirc-essderc2017.org

ESSCIRC–ESSDERC annual Conference is the most important European forum for the presentation and discussion of recent advances in solid-state devices and circuits: MAKE SURE TO BE PART OF IT!


LOCAL SCIENTIFIC SECRETARIAT
​Cor Claeys (imec, BE) | General Chair
Chantal Deboes (imec, BE) | ESSDERC Chair
Danielle Vermetten (KU Leuven, BE) | ESSCIRC Chair

ORGANIZERS   

TECHNICAL CO-SPONSORSHIP
ESSDERC FINANCIAL SPONSOR 
ESSCIRC FINANCIAL SPONSOR 
DIAMOND SPONSOR  

ORGANIZING SECRETARIAT: Sistema Congressi s.r.l. 










Feb 16, 2015

ESSCIRC/ESSDERC 2015 website is now active

 ESSCIRC/ESSDERC 2015 website is now active: www.esscirc-essderc2015.org

 The deadline for paper submission is 2 April, 2015.
 Looking forward to seeing you in Graz!

Prof. Wolfgang Pribyl: General Chair ESSCIRC/ESSDERC 2015
Franz Dielacher, Gernot Hueber: ESSCIRC TPC Chairs
Martin Schrems, Tibor Grasser: ESSDERC TPC Chairs

Jun 11, 2014

ESSDERC/ESSCIRC 2014 - Full conference program is now available

The technical programtutorial program, and workshop program of ESSDERC/ESSCIRC 2014
are now available at  ESSDERC/ESSCIRC 2014  website: http://www.esscirc-essderc2014.org 

Please remember to register to the conference and book a hotel room at before June 20, after 
which we cannot guarantee that you will find a hotel room at our rebated prices.
The event is technically co-sponsored by the
    IEEE Electron Device Society,
    IEEE Solid-State Circuit Society
    IEEE Circuits and Systems Society


We hope to see you in Venice

Best Regards
  Gaudenzio Meneghesso
ESSDERC/ESSCIRC 2014  General Chair

Roberto Bez and Paolo Pavan
ESSDERC 2014 TPC Chairs

Pietro Andreani and Andrea Bevilacqua 
ESSCIRC
 
2014 TPC Chairs


JOINT PLENARY TALKS 
Scott DeBoer
, Micron, ID, USA, A Semiconductor Memory Manufacturing and Development Perspective
Thomas H. Lee
, Stanford University, CA, USA Terahertz Electronics: The Last Frontier 
Fabio Marchiò
, STMicroelectronics, Italy, Automotive Electronics: Application & Technology Megatrends
Walter Snoeys
, CERN, Switzerland, How Chips Helped Discover the Higgs Boson at CERN
An Steegen
, IMEC, Belgium, Logic Scaling Beyond 10nm, a Power-Performance-Area-Cost Trade-off 
Sehat Sutardja
, Marvell Semiconductor, CA, USA Tremendous Benefits of Moore’s Law Have Yet to Come
ESSCIRC PLENARY TALKS
Hooman Darabi
, Broadcom Corporation, CA, USA Blocker Tolerant Software Defined Receivers
Un-Ku Moon, Oregon State University, OR, USA Emerging ADCs
Kathleen Philips
, IMEC-Holst Centre, The Netherlands Ultra-Low Power Short Range Radios
ESSDERC PLENARY TALKS
Umesh Mishra
, UCSB and TRanphorm, CA, USA,  GaN-based solutions from KHz to THz 
Eric Pop, Stanford University, CA, USA, Energy Efficiency and Conversion in 1D and 2D Electronics
Takao Someya
, University of Tokyo, Japan Bionic Skins Using Flexible Organic Devices

ESSCIRC TUTORIALS
Power Management for SoCs (Full Day), Organizer: Christoph Sandner, Infineon, Austria
High Performance Amplifiers 
(Half Day), Organizer: Angelo Nagari, STMicroelectronics, France
Phase Noise: from Fundamentals to Circuit Aspects (Half Day) Organizer: Christian Enz, EPFL, Switzerland
ESSDERC TUTORIALS
CMOS Technology at the nm Scale Era 
(Full Day) Organizer: Maud Vinet, CEA LETI, France
RRAM: from Technology to Applications (Half Day) Organizer: Bogdan Govoreanu, IMEC, Belgium 
3D: from Technology to Applications 
(Half Day) Organizer: Pascal Vivet, CEA LETI, France

ESSDERC/ESSCIRC Workshops
Beyond-CMOS for advanced More Moore and More than Moore applications
 
Organizers: Francis Balestra and Enrico Sangiorgi, Sinano Institute - Grenoble INP/CNRS, France
MOS-AK: Over Two Decades of Enabling Compact Modeling R&D Exchange   
Organizer: Wladek Grabinski, MOS-AK Group (EU),
Status of the GaN and SiC based device development
   
Organizer: Enrico Zanoni, University of Padova, DEI, Italy
THz-Workshop: Millimeter- and Sub-Millimeter-Wave circuit design and characterization
   
Organizer: Thomas Zimmer, University Bordeaux, France
Marie Curie ATWC
   
Organizer: Rinaldo Castello, University of Pavia and Marvell, Italy

Apr 3, 2014

ESSDERC/ESSCIRC 2014 - Paper submission deadline extension

the Organizing Committee decided to extend the paper submission deadline of the 44th ESSDERC and 40th ESSCIRC to:
April 16th, 2014 23:59 (GMT - 07:00 am)

This is a hard deadline and no further extensions will be granted. After the deadline is elapsed, further paper submissions will not be accepted. The notification of paper acceptance, May 27, 2014, has not changed. Detailed information about the conferences is provided at the ESSCIRC/ESSDERC 2014 website.

[read more...]

Jul 24, 2012

[mos-ak] Final Program: 10th MOS-AK/GSA ESSDERC/ESSCIRC Workshop in Bordeaux, Sept. 21, 2012

Together with the Organizing Committee, Extended MOS-AK/GSA TPC Committee, and the IEEE EDS French Branch, the technical program sponsor, as well as with the industrial sponsors Agilent Technologies, LFoundry, CSEM, STM, AMS we have pleasure to invite to the 10th MOS-AK/GSA Compact Modeling Workshop at the ESSDERC/ESSCIRC Conference in Bordeaux, Sept. 21, 2012.  

The final workshop program is available on-line: <http://mos-ak.org/bordeaux/

To register please visit official ESSDERC/ESSCIRC registration website.

- with regards - WG (for the MOS-AK/GSA Committee
––––––––––––––––––––––––––––––––––---------------- 
MOS-AK/GSA Bordeaux (F) Sept.21, 2012 
MOS-AK/GSA San Francisco, CA Q4 2012 
––––––––––––––––––––––––––––––––––----------------