[paper] Flexible Megahertz Organic Transistors

Jakob Leise^1,4, Jakob Pruefer^1,4, Ghader Darbandy¹, Aristeidis Nikolaou^1,4, Michele Giorgio², Mario Caironi², Ute Zschieschang³, Hagen Klauk³, Alexander Kloes¹, Benjamin Iñiguez⁴

and James W. Borchert⁵

Flexible megahertz organic transistors and the critical role of the device geometry on their dynamic performance

Journal of Applied Physics 130, 125501 (2021); 

DOI: 10.1063/5.0062146

  
1NanoP, TH Mittelhessen University of Applied Sciences, Gießen 35390, Germany
2Center for Nano Science and Technology @PoliMi, Istituto Italiano di Tecnologia, Milano 20133, Italy
3Max Planck Institute for Solid State Research, Stuttgart 70569, Germany
4DEEA, Uniersitat Rovira i Virgili, Tarragona 43007, Spain
5Georg August University of Goettingen, Goettingen 37077, Germany
  

Abstract: The development of organic thin-film transistors (TFTs) for high-frequency applications requires a detailed understanding of the intrinsic and extrinsic factors that influence their dynamic performance. This includes a wide range of properties, such as the device architecture, the contact resistance, parasitic capacitances, and intentional or unintentional asymmetries of the gate-to-contact overlaps. Here, we present a comprehensive analysis of the dynamic characteristics of the highest-performing flexible organic TFTs reported to date. For this purpose, we have developed the first compact model that provides a complete and accurate closed-form description of the frequency-dependent small-signal gain of organic field-effect transistors. The model properly accounts for all relevant secondary effects, such as the contact resistance, fringe capacitances, the subthreshold regime, charge traps, and non-quasistatic effects. We have analyzed the frequency behavior of low-voltage organic transistors fabricated in both coplanar and staggered device architectures on flexible plastic substrates. We show through S-parameter measurements that coplanar transistors yield more ideal small-signal characteristics with only a weak dependence on the overlap asymmetry. In contrast, the high-frequency behavior of staggered transistors suffers from a more pronounced dependence on the asymmetry. Using our advanced compact model, we elucidate the factors influencing the frequency-dependent small-signal gain and find that even though coplanar transistors have larger capacitances than staggered transistors, they benefit from substantially larger transconductances, which is the main reason for their superior dynamic performance.

Fig: Schematic cross-section of a top-contact (TC) organic TFT. Here, the semiconductor layer separates the source and drain contacts from the gate dielectric and thus from the gate-field-induced charge-carrier channel; hence, these transistors are also referred to as staggered TFTs. The overlap regions are assumed as a series connection of two capacitances. However, when the organic semiconductor (OSC) is operated in accumulation, the accumulation charges change the behavior of the series connection. The charge density at the source end of the channel is assumed to be found in the entire gate-to-source overlap region. 

Acknowledgments: The authors thankfully acknowledge funding for this project from the German Federal Ministry of Education and Research (“SOMOFLEX,” No. 13FH015IX6) and EU H2020 RISE (“DOMINO,” No. 645760), and the German Research Foundation (DFG) under Grant Nos. KL 1042/9-2, KL 2223/6-1, and KL 2223/6-2 (SPP FFlexCom). The authors would like

[paper] SiC MOSFET SPICE Model

Lefdal Hove, Haavard, Ole Christian Spro, Giuseppe Guidi

and Dimosthenis Peftitsis

Improved SiC MOSFET SPICE Model to Avoid Convergence Errors

Materials Science Forum 1004 (July 2020): 856–64

DOI: 10.4028/www.scientific.net/msf.1004.856

Abstract: This paper presents improvements to a SPICE model for a commercially available SiC MOSFET to avoid convergence errors while still providing reliable simulation results. Functionality in the internal part of the model that shapes the transconductance of the device according to its junction temperature and gate-source voltage dependency has been improved to provide a continuous characteristic rather than the initial discontinuous performance. Furthermore, the output characteristics from the initial and the proposed model have been compared to lab measurements of an actual device. The results show that the proposed and initial model provide equally reliable simulation results. However, the proposed model does not run into convergence problems.

References 

[1] X. She, A. Huang, O. Lucia, and B. Ozpineci, Review of Silicon Carbide Power Devices and Their Applications, IEEE Transactions on Industrial Electronics, vol. 64, no. 10, p.8193–8205, (2017).

[2] J. Rabkowski, D. Peftitsis, and H. P. Nee, Silicon carbide power transistors: A new era in power electronics is initiated, IEEE Industrial Electronics Magazine, vol. 6, no. 2, p.17–26, (2012).

[3] A. Stefanskyi, L. Starzak, A. Napieralski, and M. Lobur, Analysis of SPICE models for SiC MOSFET power devices,, 2017 14th CADSM 2017 - Proceedings, p.79–81, (2017).

[4] H. L. Hove, O. C. Spro, D. Peftitsis, G. Guidi, and K. Ljøkelsøy, Minimization of dead time effect on bridge converter output voltage quality by use of advanced gate drivers, 2019 10th ICPE 2019 ECCE Asia, (2019).

[5] N. Mohan, T. Undeland, and W. Robbins, Power Electronics; Converters, Applications, and Design, third ed., Wiley, (2003).

[6] C. Enz, F. Krummenacher, and E. Vittoz, An Analytical MOS Transistor Model Valid in All Regions of Operation and Dedicated to Low-Voltage and Low-Current Application, Analog Integrated Circuits and Signal Processing, vol. 8, p.83–114, (1995).

[7] M. Bucher, C. Lallement, C. Enz, F. Théodoloz, and F. Krummenacher, The EPFL-EKV MOSFET Model Equations for Simulation Technical Report V2.6,, EPFL, Lausanne, Switzerland, (1999).

[8] B. N. Pushpakaran, S. B. Bayne, G. Wang, and J. Mookken, Fast and accurate electro-thermal behavioral model of a commercial SiC 1200V, 80 mΩ power MOSFET,, Digest of Technical Papers IEEE IPPC, vol. 2015-Octob, p.1–5, (2015).

conference paper reached 700 reads

M. Bucher, A. Bazigos and W. Grabinski, "Determining MOSFET Parameters in Moderate Inversion," 2007 IEEE Design and Diagnostics of Electronic Circuits and Systems, Krakow, 2007, pp. 1-4.

Abstract: Deep submicron CMOS technology scaling leads to reduced strong inversion voltage range due to non-scalability of threshold voltage, while supply voltage is reduced. Moderate inversion operation therefore becomes increasingly important. In this paper, a new method of determining MOSFET parameters in moderate inversion is presented. Model parameters are determined using a constant current bias technique, where the biasing current is estimated from the transconductance-to-current ratio. This technique is largely insensitive to mobility effects and series resistance. Statistical data measured on 40 dies a 0.25 um standard CMOS technology are used for the illustration of this method.

[ESSCIRC 2015] Low-power analog RF circuit design based on the inversion coefficient

[ref] Enz, Christian; Chalkiadaki, Maria-Anna; Mangla, Anurag, "Low-power analog/RF circuit design based on the inversion coefficient," in ESSCIRC 2015 - 41st , vol., no., pp.202-208, 14-18 Sept. 2015

Abstract: This paper discusses the concept of the inversion coefficient as an essential design parameter that spans the entire range of operating points from weak via moderate to strong inversion, including velocity saturation. Several figures-of-merit based on the inversion coefficient, especially suitable for the design of low-power analog and RF circuits, are presented. These figures-of-merit incorporate the various trade-offs encountered in analog and RF circuit design. The use of the inversion coefficient and the derived figures-of-merit for optimization and design is demonstrated through simple examples. Finally, the simplicity of the inversion coefficient based analytical models is emphasized by their favorable comparison against measurements of a commercial 40-nm bulk CMOS process as well as with simulations using the BSIM6 model.

Keywords: Analytical models, Integrated circuits, Noise, Radio frequency, Silicon, Transconductance, Transistors, BSIM6

URL / doi: 10.1109/ESSCIRC.2015.7313863