[ESSDERC/ESSCIRC 2022] Call for Papers

Paper submission is open!

Submission deadline: Apr 12, 2022 23:59 (GMT -0700)

Decision notification: May 31, 2022 23:59 (GMT -0700)

The aim of ESSCIRC and ESSDERC is to provide an annual European forum for the presentation and discussion of recent advances in solid-state devices and circuits. The level of integration for system-on- chip design is rapidly increasing. This is made available by advances in semiconductor technology. Therefore, more than ever before, a deeper interaction among technologists, device experts, IC designers and system designers is necessary. While keeping separate Technical Program Committees, ESSCIRC and ESSDERC are governed by a common Steering Committee and share Plenary Keynote Presentations and Joint Sessions bridging both communities. Attendees registered for either conference are encouraged to attend any of the scheduled parallel sessions, regardless to which conference they belong.

PAPER SUBMISSION
Manuscript guidelines as well as instructions on how to submit electronically will be available on this website. Papers must not exceed four A4 pages with all illustrations and references included.

THE PAPERS SUBMISSION DEADLINE: APRIL 12, 2022

Papers submitted for review must clearly state:

•The purpose of the work

•How and to what extent it advances the state-of-the art

•Specific results and their impact

Only work that has not been previously published or submitted elsewhere will be considered. Submission of a paper for review and subsequent acceptance is considered as a commitment that the work will not be publicly available prior to the conference. After selection of papers, the authors will be informed about the decision of the Technical Program Committee by e-mail by 31 May 2022.

At the same time, the complete program will be published on the conference website. A binary feedback (accepted/rejected) with no comments will be provided to the authors. An oral presentation will be given at the Conference for each accepted paper. No-shows will result in the exclusion of the papers from any conference related publication. The submitted final PDF files should be IEEE Xplore compliant.

C4P: Reliability of CMOS Logic, Memory, Power and Beyond CMOS Devices

Call for Papers for a Special Issue 

of IEEE Transactions on Electron Devices

on “Reliability of CMOS Logic, Memory, Power and Beyond CMOS Devices”

Submission deadline: March 31, 2019; Publication date: October 2019

Reliability of electronic devices continues to remain as a serious issue for several technology generations. Bias Temperature Instability (BTI) continues to impact CMOS logic devices for High-K Metal Gate (HKMG) technologies, while Hot Carrier Degradation (HCD) and Self Heating Effect (SHE) have evolved as additional issues for FinFETs. The Time Dependent Dielectric Breakdown (TDDB) is still a concern and needs attention. These topics are also of interest for future devices with different channel materials (such as SiGe, Ge or III-V) and architectures (such as Gate All Around Nano Sheet FETs). The mechanisms governing degradation of program/erase window with cycling, data retention before and after cycling, etc. in conventional Vertical NAND and different emerging memories such as Resistive RAM, Phase Change RAM, Magnetic RAM and Ferroelectric RAM are of interest. Different power devices (Si and SiC FETs, IGBTs, GaN HEMTs) are becoming mainstream now and their reliability needs to be accessed. Finally, very little has been studied on the reliability of futuristic 2D channel devices.

This Special Issue of the IEEE Transactions on Electron Devices will feature the most recent developments and the state of the an in the field of device reliability based on both experimental results and theoretical models. Papers must be new and present original material that has not been copyrighted, published or accepted for publications in any other archival publications, that is not currently being considered for publications elsewhere, and that will not be submitted elsewhere while under considerations by the Transactions on Electron Devices.

Topics of interest include, but are not limited to:

• Advanced Transistors: Negative and Positive Bias Temperature Instabilities; Hot Carrier Degradation; SelfHeating Effects; De-convolution of BTI-HCI-SHE; Variability; Random Telegraph Noise; Alternative (SiGe, Ge and III-V) channels; Novel device architectures; etc.;
• Gate Dielectrics: Charge trapping and breakdown including TDDB; Reliability of novel gate dielectrics and materials for logic and memory devices; Evaluation and modeling of progressive breakdown; Gate dielectric reliability on SiGe, Ge and III-V channels; etc.;
• Reliability of Memory Devices: DRAM and NVM including 2D and 3D NAND; Novel memory devices such as Re-RAM, Phase Change RAM, MRAM; etc.;
• Power Devices: MOSFET, HEMT, IGBT on different materials (GaN, SiC, Ga203); etc.;
• RF Devices: High frequency effects; GaN HEMT; RF 801 etc.
• Novel Devices: Negative Capacitance FETs; Ferroelectric memory FETs; Tunnel FETs; Transistors with 2D semiconductors (graphene, M082); Spintronic devices; Neuromorphic devices, etc.;
• Process-Related Reliability: Reliability issues related to different fabrication processes and layout for the above devices.
• Device-Circuit Correlation: Impact of device reliability on circuit operation including any correlation between different effects; development of compact models; circuit simulation; etc.

Submission instructions: Manuscripts should be submitted in a double column format using an IEEE style file. Please visit the following link to download the templates:
http://www.ieee.org/publications_standards/pub1ications/authors/author_templates.html

In your cover letter, please indicate that your submission is for this special issue.

Submission deadline: March 31, 2019 Publication date: October 2019

Guest Editors:

1. Dr. Andreas Kerber, Globalfoundries, USA
2. Dr. Chandra Mouli, Micron Technology Inc., USA
3. Prof. Durga Misra, New Jersey Institute of Technology, USA
4. Prof. Gaudenzio Meneghesso, University of Padova, USA
5. Dr. James Stathis, IBM, USA
6. Prof. Ninoslav D. Stojadinovié, University of Nis, RS
7. Dr. Randy Koval, Intel, SG
8. Prof. Souvik Mahapatra, Indian Institute of Technology, Bombay, IN (Guest EIC)
9. Dr. Stephen Ramey, Intel, USA
10. Prof Tibor Grasser, TU, Wien, A

(NEW DEADLINE: 10 APRIL) ESSDERC Call for Papers

Call for Papers 

(NEW DEADLINE: 10 APRIL) 

PAPER SUBMISSION: Manuscript guidelines as well as instructions on how to submit electronically ARE AVAILABLE HERE. Papers must not exceed four A4 pages with all illustrations and references included. All submissions must be received by (NEW DEADLINE): 10 APRIL

Papers submitted for review must clearly state:

• The purpose of the work
• How and to what extent it advances the state-of-the-art
• Specific results and their impact

Only work that has not been previously published or submitted elsewhere will be considered. Submission of a paper for review and subsequent acceptance is considered as a commitment that the work will not be publicly available prior to the conference [read more...]

[paper submission] MIXDES 2018

This year the 25th International Conference "Mixed Design of Integrated Circuits and Systems", MIXDES 2018 will take place on June 21-23, 2018 in Gdynia, Poland

Submit a paper <https://www.mixdes.org/Mixdes3/>

[C4P] IEDM 2017

2017 IEDM CALL FOR PAPERS

The Annual International Electron Devices Meeting will be held at the Hilton San Francisco Union Square San Francisco, CA December 2-6, 2017

Abstract Deadline (four page final paper): August 2nd, 2017

To provide faster dissemination of the conference’s cutting-edge results, the abstract submission deadline has been moved to August 2nd for submission of four-page, camera-ready abstracts. Accepted papers will be published as-is in the proceedings

A Call for Papers flyer is available here: IEDM 2017 Call For Papers.

Customized Call for Papers for each of the technical subcommittee areas are also available:

• Circuit and Device Interaction (CDI)
• Characterization, Reliability, and Yield (CRY)
• Compound Semiconductor and High Speed Devices (CHS)
• Memory Technology (MT)
• Modeling and Simulation (MS)
• Material and interface modeling 
• Compact models
• Kinetic Monte Carlo and Molecular Dynamics
• Reliability and variability modeling
• Technology benchmarking
  New or trending areas include:
• First principle based quantum transport
• Process simulation with atomistic methods
• Self heating, interconnect and packaging
• Nano Device Technology (NDT)
• Optoelectronics, Displays, and Imagers (ODI)
• Power Devices (PD)
• Process and Manufacturing Technology (PMT)
• Sensors, MEMS, and BioMEMS (SMB)

[Call for Papers] ESSCIRC–ESSDERC 2017

September 11-14, 2017

LEUVEN - Belgium
www.esscirc-essderc2017.org

ESSCIRC–ESSDERC annual Conference is the most important European forum for the presentation and discussion of recent advances in solid-state devices and circuits: MAKE SURE TO BE PART OF IT!

CALL for PAPERS

GUESS WHO IS COMING!

LOCAL SCIENTIFIC SECRETARIAT
​Cor Claeys (imec, BE) | General Chair
Chantal Deboes (imec, BE) | ESSDERC Chair
Danielle Vermetten (KU Leuven, BE) | ESSCIRC Chair

ORGANIZERS   

TECHNICAL CO-SPONSORSHIP
ESSDERC FINANCIAL SPONSOR 
ESSCIRC FINANCIAL SPONSOR 
DIAMOND SPONSOR  

ORGANIZING SECRETARIAT: Sistema Congressi s.r.l. 

MNF2016 CALL FOR ABSTRACTS

MNF2016 

CALL FOR ABSTRACTS 

(Extended Deadline to 8 April 2016)

Following numerous requests, we [MNF TPC] have decided to base the proceedings on extended abstracts (of 1-2 pages length) instead of longer proceedings papers. You are not requested to submit a 6-8 pages proceedings paper now.

Those of you who have already submitted your abstracts have the opportunity to extend them to 2 pages to include 1 or 2 figures or tables, if you so wish.

We will keep the abstract submissions open now until the 8 April 2016. Again, submissions need to be pdfs. The extended abstracts should follow the formatting guidelines given in the proceedings paper template given on the webpage.

[read more]

IEEE TED Call for Papers: Variation aware technology and circuit codesign

 Call for papers for a special issue of 

 IEEE Transactions on Electron Devices 

"Variation aware technology and circuit codesign" 

The special issue on "variation aware technology and circuit co design is devoted to the research and development activities on variation aware process device technology and co-optimization with circuit design. Rapid pace of new technology introduction to CMOS technology requires much more sophisticate optimization of process, device, and circuit design, in order to maximize return on investment. Careful optimization of process technology, device structure, layout and circuit design in holistic manner enables significant performance improvement while reducing overall power consumption with least amount of area penalty.

Among many challenges for this holistic optimization, higher process and device variation becomes one of most critical issues as process technology is marching into below 20nm node.

New material technology and non-planar device structure add additional variation source on top of conventional geometrical effect. Not only reducing extrinsic portion of variation is important understanding the effect of such variation in various actual circuit design is also very important In addition to addressing variation at individual process and design element, this special edition also touches on the impact of variation aware optimization to overall SOC design that requires both high performance and low power functional blocks.

This special edition includes, but not limited to, following topics:

• Variation reduction methods of advanced process technology, including patterning, deposition and etch processes
• Variation reduction methods of dvanced device technology, including FinFET, Nanowire, FDSOL etc.
• Co-optimization of technology and circuit to minimize variation and/orimpact of variation.
• ТCAD to understand the source of variation and provide practical method to improve.
• Novel process and device technology to cope with variation issue in coming nodes.
• SOC integration and design methodology to take process device variation into account.

Please submit papers by using the website: https://mc.manuscriptcentral.com/ted link here

BE SURE TO MENTION THE SPECIAL ISSUE WITHIN THE COVER LETTER

Submission Deadline: October 31, 2014
Scheduled Publication Date: June 2015

Guest Editors:
Stanley S.C. Song Qualcomm
Huiling Shang, IBM
Каustav Banerjee, University of California, Santa Barbara
Shuji Ikeda, TEI solution

If you have any questions about submitting a manuscript, please contact:
Jo Ann Marsh (j.marsh@ieee.org) T-ED Special Issues Administrative Support

IJNM Call for Papers

Advances in simulation-driven modeling and optimization of microwave/RF circuits

IJNM Call for Papers

Computer-aided modeling and design of microwave/radio frequency (RF) devices and circuits have undergone tremendous developments in the past decade. The complexity of today's devices and circuits renders electromagnetic (EM) simulation a sine qua non in the microwave design process. That said, EM-driven design poses significant challenges, mostly due to the high computational cost of accurate, high-fidelity simulation. The availability of massive computational resources does not always translate into design speedup because of the need to account for interactions between devices and their surroundings as well as multi-physics (e.g., EM-thermal) effects. Not surprisingly, traditional design optimization procedures that directly utilize EM-simulated responses typically fail or are impractical. As a consequence, there is growing interest in alternative optimization and modeling methodologies, especially ones that exploit computationally cheap surrogate models.

This Special Issue focuses on the current state of the art and future directions in microwave and RF design. Papers on software engineering and practical applications aspects are also encouraged. Suitable topics for this Special Issue therefore include but are not limited to

• surrogate-based modeling and optimization methods including space mapping;
• knowledge-based and tuning methodologies;
• global optimization, evolutionary algorithms, particle swarm optimization, and so on;
• multi-objective optimization;
• adjoint-sensitivities for efficient gradient-based optimizers;
• optimization techniques for nonlinear circuits;
• software architectures for optimization-oriented design;
• automated design optimization using EM simulators;
• optimization for inverse EM problems;
• neural network approaches; and
• optimization for discrete problems.

Manuscripts for this Special Issue should adhere to the requirements for regular papers of the IJNM as specified in the Author Guidelines at http://onlinelibrary.wiley.com/journal/10.1002/(ISSN)1099-1204/homepage/ForAuthors.html

Potential contributors may contact the guest editor to determine the suitability of their contribution to the Special Issue. All manuscripts should be submitted via the IJNM's manuscript website http://mc.manuscriptcentral.com/ijnm, with a statement that they are intended for this Special Issue.

Manuscript submission deadline: January 31, 2015

Prof. Slawomir Koziel
Engineering Optimization and Modeling Center, 
School of Science and Engineering, 
Reykjavik University, Reykjavik, Iceland

1. 
   

[Call for Papers] SISPAD2014

https://sites.google.com/site/sispad2014/

This is a call for papers for the 2014 International Conference on Simulation of Semiconductor Processes and Devices (SISPAD2014), to be held September 9-11, 2014, in Yokohama, Japan. This conference provides an opportunity for the presentation and discussion of the latest advances in modeling and simulation of semiconductor devices, processes, and equipment for integrated circuits.

Abstract submission deadline is March 31, 2014.

Workshops:
Two companion workshops will run concurrently prior to the start of the conference on Monday 8th September 2014:

• Workshop 1: Compact Modeling -Enabling Better Insight of Device Features-
  Organizer: Mitiko Miura-Mattausch (Hiroshima University)
• Workshop 2: Carrier Transport in Nano-MOS Transistors: Theory and Experiments(tentative)
  Organizer: Hideaki Tsuchiya (Kobe University) and Yoshinari Kamakura (Osaka University)

Plenary Speakers:

• Augusto Benvenuti (Micron Technology)
  Current status and future prospects of non-volatile memory modeling
• Massimo V. Fischetti (University of Texas at Dallas)
  Physics of electronic transport in low-dimensionality materials forfuture FETs
• Kimimori Hamada (Toyota Motor Corporation)
  TCAD challenge on development of power semiconductor devices for automotive applications

Invited Speakers:

• Mario Ancona (Naval Research Laboratory)
  Nonlinear thermoelectroelastic simulation of III-N devices
• Asen Asenov (University of Glasgow)
  Progress in the simulation of time dependent statistical variability in nano CMOS transistors
• Jean-Pierre Colinge (Taiwan Semiconductor Manufacturing Company)
  Nanowire transistors: pushing Moore's law to the limit
• Tibor Grasser (Vienna University of Technology)
  Advanced modeling of charge trapping: RTN, 1/f noise, SILC, and BTI
• Kohji Mitsubayashi (Tokyo Medical and Dental University)
  Novel biosensing devices for medical applications
• Christian Sandow (Infineon Technologies)
  Exploring the limits of the safe operation area of power semiconductor devices
• Mark Stettler (Intel Corporation)
  Device and process modeling: 20 years at Intel's other fab

Call for IJNM papers: Noise modeling of high-frequency semiconductor devices

INTERNATIONAL JOURNAL OF NUMERICAL MODELLING: ELECTRONIC NETWORKS, DEVICES AND FIELDS Int. J. Numer. Model. (2014)

Call for IJNM papers: Noise modeling of high-frequency semiconductor devices 

Noise processes in solid-state active devices often determine their fundamental operational limits. This is especially true in situations where a device operates under tight sensitivity and accuracy constraints, as is the case in satellite communication systems, aerospace instrumentation, and deep-space radio astronomy. Today’s ultra-high frequency transistors that meet these demanding low-noise performance characteristics often leverage progressive device downscaling techniques in conjunction with improved semiconductor alloys. 

To enable the design of next-generation low-noise devices, however, accurate and flexible models that characterize the connection between the physics of microscopic noise processes and measurable macroscopic performance are called for. The objective of this Special Issue is to collect and disseminate recent results addressing the topic of modeling and simulation of the macroscopic noise performance of high- frequency transistors including but not limited to GaAs-based and GaN-based field-effect transistors, Si metal–oxide–semiconductor FETs and FinFETs, InP-based high-electron-mobility transistors, and GaAs and SiGe heterojunction bipolar transistors. It is worth pointing out that because of frequency up-conversion phenomena caused by a device’s nonlinearities, low frequency noise processes may strongly impact microwave and millimeter wave behavior as well. Contributions focusing on low-frequency noise modeling therefore will be considered as well. 

This issue will include both invited and contributed manuscripts.

Manuscripts for this Special Issue should adhere to the requirements for regular papers of the IJNM as specified in the Author Guidelines at 

http://onlinelibrary.wiley.com/journal/10.1002/(ISSN)1099-1204/ homepage/ForAuthors.html. 

Potential contributors may contact the Guest Editors to determine the suitability of their contribution to the Special Issue. All manuscripts should be submitted via the IJNM’s manuscript website, with a statement that they are intended for this Special Issue. 

Guest Editors: 
Prof. Alina Caddemi University of Messina, Italy Email:
Prof. Ernesto Limiti University of Rome Tor Vergata, Italy Email:

Manuscript submission deadline: July 31, 2014

TED Call for Papers on Compact Modeling of Emerging Devices

Compact Models (CMs) for circuit simulation have been at the heart of CAD tools for circuit design for almost five decades. As the mainstream CMOS technology is scaled into the nanometer regime, development of a truly physical and predictive CM for circuit simulation that covers geometry, bias, temperature, DC, AC, RF, and noise characteristics becomes a major challenge. The last call for a special issue on “advanced compact models and 45-nm modeling challenges” was in 2005. Seven years have passed, new technology nodes have been implemented, compact models have evolved and new compact models as well as compact models for new devices are being developed. Therefore, there is a need for another special issue dedicated to the advancement and challenges in core field-effect transistor (FET) models for 32-nm technologies and beyond as well as emerging technologies. For the core FET models, the associated noise/mismatch and reliability/variability models as well as proximity effects have become an essential part of the modeling effort. High-frequency, high-voltage, high-power, high-temperature devices have been extensively investigated, and their CMs are being reported in the literature. Device/circuit interaction and layout-dependent proximity effects are also hot topics today that are essential in nanometer chip designs. It is timely to report advances in these CMs in the 32-nm/22-nm technology era.

Concurrently, nonclassical MOSFETs as well as their CMs, such as multigate FinFETs and nanowire FETs, partially/fully-depleted ultrathin body (UTB) SOT, and thin-film transistors (TFTs), have emerged over the past decades. With the announcement of FinFETs being used in 22-nm and sub-22nm technology nodes, the need for such core models for fabless designers becomes an urgent reality. In these nonclassical devices, transistors are essentially short-channel, narrow-width, and thin-body. Tt is also an interesting topic to discuss and debate on the two different formalisms “top-down” drift-diffusion formulation adding ballistic effects versus “bottom-up” quasi-ballistic formulation adding scattering effects for modeling the real devices that are somewhere in between. Heterogeneous integration of various devices into the CMOS platform also becomes an important trend.

In addition, it is also timely to report advances in CMs of emerging devices beyond traditional silicon CMOS, such as different materials (III-V/Ge channel, organic) and different source/drain injection mechanisms (Schottky-barrier, tunneling, and junctionless FETs). These emerging device options for future VLSI building blocks have been studied extensively, while good physical CMs are still lacking. The special issue in these topics will stimulate research and development to promote modeling efforts such that theory would lead and guide technology realization and selection for future generations.

The special issue for the TRANSACTIONS ON ELECTRON DEVICES on compact modeling of emerging devices is devoted to the review and report of advancements in CMs for 32-nm technologies and beyond, including bulk and nonclassical CMOS and their associated noise/mismatch and reliability/variability models, as well as various emerging devices as future generation device options. It is timely as the industry is in the transition from traditional planar bulk-CMOS towards vertical FinFET technologies, and exploration of heterogeneous integration with various materials and structural choices.

Please submit manuscripts by using the following URL: http://mc.manuscriptcentral.com/ted

MAKE SURE TO MENTION THE SPECIAL ISSUE IN THE COVER LETTER

Paper submission Deadline: June 30, 2013

Scheduled Publication Date: February 2014

Guest Editors:

Xing Zhou, Nanyang Technological University, 

Jamal Deen, McMaster University, 

Benjamin Iniguez, Universitat Rovira i Virgili, 

Christian Enz, Swiss Federal Institute of Technology, 

Rafael Rios, Intel Corp.

If you have any questions about submitting a manuscript, please contact:

Jo Ann Marsh 

IEEE EDS Publications Office

445 Hoes Lane Piscataway JN 08854

Phone: +1 732 562 6855

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Digital Object Identifier 10.1109/TED.2013.2253418

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C4P: 2012 IEEE Silicon Nanoelectronics Workshop

Hilton Hawaiian Village in Honolulu, Hawaii (June 10-11, 2012)
Sponsored by the IEEE Electron Device Society

Authors are encouraged to submit a full-length paper to the IEEE Transactions on Nanotechnology or the IEEE Transactions on Electron Devices. Download the Call for Papers (PDF format) Further Information The 2012 Silicon Nanoelectronics Workshop is a satellite workshop of the 2012 VLSI Symposia sponsored by the IEEE Electron Device Society. It will be held on June 10-11, 2012 at the Hilton Hawaiian Village in Honolulu, Hawaii USA. This will be the seventeenth workshop in the annual series. Original papers on nanometer-scale devices and technologies which utilize silicon or which are based on silicon substrates are welcome. Prospective authors are requested to submit an abstract in PDF format, consisting of one page of text and one page of figures. It must include the paper title, the authors’ names and affiliation(s), and the full contact information (mailing address, phone and FAX numbers, e-mail address) for the corresponding author. Accepted abstracts will be reproduced in the workshop proceedings exactly as received. Some of the accepted papers will be presented in Poster Sessions. The deadline for receipt of abstracts is 5PM (Pacific Time) April 1, 2012. Authors will be notified by April 30, 2012.

Registration forms and hotel reservation forms will be provided in the Advanced Program of the 2012 VLSI Technology Symposium (http://www.vlsisymposium.org/index.html).
Scope:
•Sub-10 nm transistors, including those employing non-classical structures, novel channel and source/drain materials, or non-thermal injection mechanisms
•Junction and insulator materials and process technology for nanoelectronic devices
•Techniques for fabrication of nanostructures, including nanometer-scale patterning
•Physics of nanoelectronic devices, e.g. quantum effects, non-equilibrium transport
•Modeling/simulation of nanoelectronic devices, e.g. including atomistic effects
•Nanoscale surface, interface, and heterojunction effects in devices
•Device scaling issues including doping fluctuations and atomic granularity
•Circuit design issues and novel circuit architectures, including quantum computing, for nanoelectronic devices
•Optoelectronics using silicon nanostructures
•Techniques targeting zero power electronics (self-supplying), including wireless sensors, energy harvesting, steep slope devices, ultra-low power design and devices
•Devices for heterogeneous integration on silicon, including Graphene, III-V devices, CNT, spin-based devices, MEMs and NEMS, etc.
[read more...]

8th International Conference on Devices, Circuits and Systems (ICCDCS)

ICCDCS is an IEEE-EDS technically sponsored international conference biannually held since its first edition (Caracas, 1995) at different locations within the Caribbean basin. Over time this conference has acquired a prestigious position as the outstanding international IEEE conference dealing with Electron Devices and Circuits and Systems which takes place within the Latin American Region.

Its main objective is to serve as a significant meeting point and technical forum to initiate, renew and maintain direct personal relations aimed at sharing relevant technical know-how among Latin American and rest-of-the-world professionals involved in the disciplines that it covers. Industry, Universities and R&D Institutions are invited to participate. English is the official working language of the Conference, although Spanish and Portuguese are also freely used in informal communications.

Prospective authors are invited to submit contributions for oral presentations to be reviewed by the Technical Program Committee. They should deal with new results, relevant ideas or innovations that advance the state-of-the-art in the areas of the Technical Program. Topics may span from basic theory to industrial applications, research, development, design, technology and applications of electron devices, analysis, design, and practical implementation of circuits, and their application to power electronics, telecommunications and instrumentation. 

Location: 

The ICCDCS'12 will be held on Playa del Carmen, México, from March 14 through March 17, 2012

You can download the pdf version of the Call for Papers here.

MIXDES 2010 paper submission deadline

The deadline for the MIXDES paper registration passes in approximately in 6 weeks (Feb 28th, 2010). The most current information about the conference, regular and special sessions invited talks etc. can be found at the in the Final Call for Papers.

This year the conference will be organized in Wroclaw, one of the oldest and most beautiful cities in Poland. It is located in southwestern Poland, 160 km from Germany and 120 km from the Czech Republic. It is well equipped with communication facilities: international airport, railways and highways, so is quite easy to get there.

As in previous years the papers should be prepared following the paper formatting requirements, however the format may be corrected till the final paper versions deadline (May 15th, 2010). The paper registration and updates should be proceeded by your personal account at the conference web page after log on.

With further questions please contact Dr. Mariusz Orlikowski, the MIXDES 2010 Conference Secretary.