Maciej Ogorzałek Candidate for 2020 IEEE Vice President-Elect for Technical Activities

To learn more about my qualifications, IEEE activities and accomplishments, please visit

http://www.doit.fais.uj.edu.pl/maciej-ogorzalek

IEEE EDS MQ at Hotel Plaza, Begumpet (IN)

Joint Chapter of Electron Devices and Circuits and Systems Societies (ED/CAS)

presents

IEEE Electron Devices Mini Colloquia

Date:  Sunday, 24 February 2019 Time:  3.00 P.M to 6.00 P.M

Venue: Hotel Plaza, Begumpet. Free Registration Link 

For any further details please contact the MQ Coordinators:

• Dr. Mohammed Arifuddin Sohel, Chair, IEEE CAS/EDS joint Chapter
• Dr. A.G. Krishna Kanth, Vice Chair, IEEE CAS/EDS joint Chapter

Registrations: 3:00PM to 3.15 PM

DL Talk 1: 3.15 PM to 4.00PM, Speaker: Prof. Charvaka Duvvury, iT2 Technologies (USA)
Topic: ESD Issues and Challenges for Advanced Semiconductor Technologies

Electro-static Discharge (ESD) has been a constant reliability concern for IC technologies for several decades and it is heading to be a roadblock to newer applications for electronic devices. The seminar will begin with a summary of the understanding about ESD and how this is applied to develop protection at the IC level for Digital, Analog, and RF circuits. This will be followed by a review of the problems posed by advanced technologies beyond the 32 nm node and the corresponding challenge of hitting the available ESD design window while meeting the IO high-speed performance requirements. The talk will conclude with a survey of the upcoming challenges from emerging technologies such as GaN and CNT, as well as IoT applications. 

Speaker Bio: Charvaka Duvvury was a Texas Instruments fellow while he worked in the Silicon Technology Development group at TI.  He received his PhD in engineering science from the University of Toledo and afterwards worked as a post-doctoral fellow in Physics at the University of Alberta. His experience at Texas Instruments spanned for 35 years in semiconductor device physics with pioneering development work in ESD design. He has also mentored PhD students at several leading US universities on their investigations in ESD research and received Outstanding Industry Mentor Award twice from the SRC. Charvaka has published over 150 papers in technical journals and conferences and holds more than US 75 patents. He co-authored and contributed to 5 books on the subject. He is a recipient of the IEEE Electron Devices Society’s Education Award and Outstanding Contributions Award from the EOS/ESD Symposium. Charvaka has been serving on Board of Directors of the ESD Association (ESDA) since 1997 promoting ESD education and research at academic institutes. He is co-founder and co-chair of the Industry Council on ESD since 2006. During 2015 he became a co-founder of the iT2 Technologies that utilizes software engine and machine learning for rapid ESD data analysis. Charvaka is also Fellow of the IEEE.

Hi Tea and Networking: 4.00 PM to 4.15 PM

DL Talk 2: 4.15 PM to 5.00PM Speaker: Dr. Wladek Grabinski, MOS-AK (Switzerland)

Topic: FOSS TCAD/EDA Process/Device Simulations for Compact/SPICE Modeling

Compact/SPICE models of circuit elements (passive, active, MEMS, RF) are essential to enable advanced IC design using nanoscaled semiconductor technologies. To explore all related interactions, we are discussing selected FOSS CAD tools along complete technology/design tool chain from nanascaled technology processes. New technology and device development will be illustrated by application examples of the FOSS TCAD tools: Cogenda TCAD and DEVSIM. Compact modeling will be highlighted by review topics related to its parameter extraction and standardization of the experimental and measurement data exchange formats. Finally, we will present FOSS CAD simulation and design tools: ngspice, Qucs, GnuCap, Xyce.

Speaker Bio: Wladek Grabinski received the Ph.D. degree from the Institute of Electron Technology, Warsaw, Poland, in 1991. From 1991 to 1998 he was a Research Assistant at the Integrated Systems Lab, ETHZ, Switzerland, supporting the CMOS and BiCMOS technology developments by electrical characterization of the processes and devices. From 1999 to 2000, he was with LEG, EPFL, and was engaged in the compact MOSFET model developments supporting numerical device simulation and parameter extraction. Later, he was a technical staff engineer at Motorola, and subsequently at Freescale Semiconductor, Geneva Modeling Center, Switzerland. He is now a consultant responsible for modeling, characterization and parameter extraction of MOST devices for the IC design. Wladek is the chair of the ESSDERC Track4: "Device and circuit compact modeling" as well as has served as a member of organization committee of ESSDERC/ESSDERC, TPC of SBMicro, SISPAD, MIXDES Conferences; reviewer of the IEEE TED, IEEE MWCL, IJNM, MEE, MEJ/ Wladek is involved in activities of the MOS-AK Association and serves as a coordinating manager since 1999.

DL Talk 3: 5.00PM to 5.45 PM Speaker: Prof. Roberto Murphy, INAOE (Mexico)
Topic: Fundamental Aspects of CMOS RF Modeling and Characterization

As CMOS technology evolves, higher frequencies can be attained while more complex functions and operations become possible in Integrated Circuits. At the design stage, there are several fundamental aspects which have to be taken into account in order to have successful fabrication results, the closest to simulation predictions as possible. Furthermore, this evolution leads to more time-consuming characterization routines, which require both personnel and time to be performed. Some of the aspects dealt with in this talk refer to characterization techniques, substrate network effects, and geometry effects.

Speaker Profile:  Roberto S. Murphy-Arteaga (M´92, SM´02) received his B.Sc. degree in Physics from St. John’s University, Minnesota, and got his M.Sc. and Ph.D. degrees from the National Institute for Research on Astrophysics, Optics and Electronics (INAOE), in Tonantzintla, Puebla, México.  He has been a researcher at INAOE since 1988. Since then, he has presented over 110 talks at scientific conferences, directed nine Ph.D. theses, 16 M.Sc. and 2 B.Sc. theses, published more than 140 articles in scientific journals, conference proceedings and newspapers, and is the author of a text book on Electromagnetic Theory.  He is currently a senior researcher with the Microelectronics Laboratory.  Dr. Murphy’s research interests are the physics, modeling and characterization of the MOS Transistor and passive components for high frequency applications, especially for CMOS wireless circuits, and antenna design.  For the last 30 years, he has been active in the organization of conferences, mostly in Latin America, such as the IEEE International Caribbean Conference on Devices, Circuits and Systems; the Latin American Symposium on Circuits and Systems; VLSI-SoC, and others related to microelectronics and IC design. He is a Senior Member of IEEE, a Distinguished Lecturer of the Electron Devices Society, the President of ISTEC, a member of the Mexican Academy of Sciences, and a member of the Mexican National System of Researchers (SNI).

IEEE Cledo Brunetti Award 2018 presented to Prof.Dr. Siegfried Selberherr

One of the founders of modern Technology Computer Aided Design (TCAD), Siegfried Selberherr has provided modeling and software development tools invaluable to the continued miniaturization of semiconductor devices. TCAD involves the use of computer simulation to develop and optimize semiconductor processing technologies. Selberherr developed MINIMOS for two-dimensional predictive simulation of the electrical characteristics of miniaturized devices to understand and control the short-channel effects and doping profiles encountered as device sizes shrink. MINIMOS was later enhanced for three-dimensional simulation to address energy transport and interface physics. He also created the ZOMBIE and PROMIS simulators, which incorporated mesh generation and programming interfaces. Selberherr then developed the Vienna Integrated System for TCAD Applications (VISTA) to combine both process and device simulation tools in a common framework. An IEEE Fellow, Selberherr is a professor with the Institute for Microelectronics at the Technische Universität Wien, Vienna, Austria.

Michael Shur winning the 2018 IEEE EDS J.J. Ebers Award

Congratulations to Prof. Michael Shur for winning the 2018 IEEE EDS J.J. Ebers Award "For pioneering the concept of ballistic transport in nanoscale semiconductor devices"

Recent Winners of the J.J. Ebers Award

2017 - Kang L. Wang "For contributions and leadership in strained SiGe and magnetic memory technologies"

2016 - Jaroslav Hynecek "For the pioneering work and advancement of CCD and CMOS image sensor technologies"

2015 - Jack Yuan-Chen Sun "For sustained leadership and technical contributions to energy efficient foundry CMOS technologies"

2014 - Joachim N. Burghartz "For contributions to integrated spiral inductors for wireless communication ICs and ultra-thin silicon devices for emerging flexible electronics"

2013 - Nobukazu Teranishi "For development of the Pinned Photodiode concept widely used in Image Sensors”

2012 - Yuan Taur "For contributions to the advancement of several generations of CMOS process technologies"

2011 - Stuart Ross Wenham “For technical contributions and successful commercialization of high efficiency solar cells”

2010 - Mark E. Law “For contributions to widely used silicon integrated circuit process modeling”

C4P: Reliability of CMOS Logic, Memory, Power and Beyond CMOS Devices

Call for Papers for a Special Issue 

of IEEE Transactions on Electron Devices

on “Reliability of CMOS Logic, Memory, Power and Beyond CMOS Devices”

Submission deadline: March 31, 2019; Publication date: October 2019

Reliability of electronic devices continues to remain as a serious issue for several technology generations. Bias Temperature Instability (BTI) continues to impact CMOS logic devices for High-K Metal Gate (HKMG) technologies, while Hot Carrier Degradation (HCD) and Self Heating Effect (SHE) have evolved as additional issues for FinFETs. The Time Dependent Dielectric Breakdown (TDDB) is still a concern and needs attention. These topics are also of interest for future devices with different channel materials (such as SiGe, Ge or III-V) and architectures (such as Gate All Around Nano Sheet FETs). The mechanisms governing degradation of program/erase window with cycling, data retention before and after cycling, etc. in conventional Vertical NAND and different emerging memories such as Resistive RAM, Phase Change RAM, Magnetic RAM and Ferroelectric RAM are of interest. Different power devices (Si and SiC FETs, IGBTs, GaN HEMTs) are becoming mainstream now and their reliability needs to be accessed. Finally, very little has been studied on the reliability of futuristic 2D channel devices.

This Special Issue of the IEEE Transactions on Electron Devices will feature the most recent developments and the state of the an in the field of device reliability based on both experimental results and theoretical models. Papers must be new and present original material that has not been copyrighted, published or accepted for publications in any other archival publications, that is not currently being considered for publications elsewhere, and that will not be submitted elsewhere while under considerations by the Transactions on Electron Devices.

Topics of interest include, but are not limited to:

• Advanced Transistors: Negative and Positive Bias Temperature Instabilities; Hot Carrier Degradation; SelfHeating Effects; De-convolution of BTI-HCI-SHE; Variability; Random Telegraph Noise; Alternative (SiGe, Ge and III-V) channels; Novel device architectures; etc.;
• Gate Dielectrics: Charge trapping and breakdown including TDDB; Reliability of novel gate dielectrics and materials for logic and memory devices; Evaluation and modeling of progressive breakdown; Gate dielectric reliability on SiGe, Ge and III-V channels; etc.;
• Reliability of Memory Devices: DRAM and NVM including 2D and 3D NAND; Novel memory devices such as Re-RAM, Phase Change RAM, MRAM; etc.;
• Power Devices: MOSFET, HEMT, IGBT on different materials (GaN, SiC, Ga203); etc.;
• RF Devices: High frequency effects; GaN HEMT; RF 801 etc.
• Novel Devices: Negative Capacitance FETs; Ferroelectric memory FETs; Tunnel FETs; Transistors with 2D semiconductors (graphene, M082); Spintronic devices; Neuromorphic devices, etc.;
• Process-Related Reliability: Reliability issues related to different fabrication processes and layout for the above devices.
• Device-Circuit Correlation: Impact of device reliability on circuit operation including any correlation between different effects; development of compact models; circuit simulation; etc.

Submission instructions: Manuscripts should be submitted in a double column format using an IEEE style file. Please visit the following link to download the templates:
http://www.ieee.org/publications_standards/pub1ications/authors/author_templates.html

In your cover letter, please indicate that your submission is for this special issue.

Submission deadline: March 31, 2019 Publication date: October 2019

Guest Editors:

1. Dr. Andreas Kerber, Globalfoundries, USA
2. Dr. Chandra Mouli, Micron Technology Inc., USA
3. Prof. Durga Misra, New Jersey Institute of Technology, USA
4. Prof. Gaudenzio Meneghesso, University of Padova, USA
5. Dr. James Stathis, IBM, USA
6. Prof. Ninoslav D. Stojadinovié, University of Nis, RS
7. Dr. Randy Koval, Intel, SG
8. Prof. Souvik Mahapatra, Indian Institute of Technology, Bombay, IN (Guest EIC)
9. Dr. Stephen Ramey, Intel, USA
10. Prof Tibor Grasser, TU, Wien, A

Hybrid Systems-in-Foil: Enabler or Flexible Electronics

Presented by: Joachim N. Burghartz

Date: 22 August 2018

Time: 11 AM – 12 PM EDT 

Hybrid Systems-in-Foil: Enabler or Flexible Electronics - Flexible electronics add mechanical flexibility, shape adaptivity and stretchability as well as large-area place ability to electronic systems, thus allowing for conquering fundamentally new markets in consumer and commercial applications. Hybrid assembly of large-area devices and ultra-thin silicon chips on flexible substrates is viewed as an enabler to high-performance and reliable industrial solutions as well as to high-end consumer applications of flexible electronics. This talk discusses issues in ultra-thin chip fabrication, device modeling and circuit design, as well as assembly and interconnects for thin chips embedded into foil substrates in which flexible large-area components are implemented for an overall optimized Hybrid System-in-Foil (HySiF).

This message is being sent to you on behalf of Tian-Ling Ren, EDS Education Committee Chair. All participants will receive WebEx details prior to the event. We sincerely hope that you can join us for these special events. Register Now!

EDS DL MQ Gdynia Maritime University, June 20, 2018, Gdynia, Poland

EDS Distinguished Lecturer Mini-Colloquium
SiC: technology, devices, modeling
Gdynia Maritime University, June 20, 2018, Gdynia, Poland
admission: free of charge

organized by:	ED Poland Chapter Gdynia Maritime University Instytut Technologii Elektronowej (ITE, Warsaw)
technical support:	Lodz University of Technology, Department of Microelectronics and Computer Science
venue:	Gdynia Maritime University ul. Morska 83, 81-225 Gdynia, Poland

9:00-9:05

Introduction

Dr. Daniel Tomaszewski, IEEE EDS Member, ITE, Warsaw

9:05-9:50 SiC technology offerings; challenges and opportunities

Lecturer: Dr. Muhammad Nawaz, IEEE Senior Member, IEEE EDS Distinguished Lecturer,
ABB Corporate Research, Sweden

Abstract: A wide bandgap SiC technology has now entered in transitional phase on various power electronics front; thanks to its superior physical properties such as wide bandgap, larger breakdown field strength, higher carrier saturation velocity, and larger thermal conductivity than that of Si counterpart. Low voltage SiC MOSFET discrete devices and power modules within voltage range of 1.2-1.7 kV are commercially available. On the other side, medium voltage MOSFET devices of 3.3-6.5 kV and high voltage MOSFET devices of 10-15 kV are also visible in the scientific literature with excellent static and dynamic performance, illustrating the potential benefit for high power applications in energy transmission and distribution networks. This talk will focus on the requirement and issues using SiC MOSFETs facing high power applications while addressing simultaneously the potential benefits for high power converters. Reliability concerns from the end user’s perspective will be addressed as well.

10:00-10:45 On the way to the Energy and Variability Efficient (E.V.E.) Era

Lecturer: Prof. Simon Deleonibus, IEEE Fellow, IEEE EDS Distinguished Lecturer, Fellow Electrochemical Society, CEA Research Director, France

Abstract: Major power consumption reduction will drive future design of technologies and architectures that will request less greedy devices and interconnect systems. The electronic market will be able to face an exponential growth thanks to the availability and feasibility of autonomous and mobile systems necessary to societal needs. The increasing complexity of high volume fabricated systems will be possible if we aim at zero intrinsic variability, and generalize 3-dimensional integration of hybrid, heterogeneous technologies at the device, functional and system levels. Weighing on the world energy saving balance will be possible and realistic by maximizing the energy efficiency of co integrated Low Power and High Performance Logic and Memory devices.The future of Nanoelectronics will face the major concerns of being Energy and Variability Efficient (E.V.E.).

10:55-11:15 Coffee break

11:15-12:00 SiC power device fabrication and path to commercialization

Lecturer: Prof. Victor Veliadis, IEEE Fellow, IEEE EDS Distinguished Lecturer, Deputy Executive Director and CTO, PowerAmerica Professor of Electrical and Computer Engineering, North Carolina State University

Abstract: The presentation will discuss major SiC power device application areas and touch on foundry models, cost reduction strategies, and path to commercialization. The advantages of SiC over other power electronic materials will be outlined, and SiC devices currently developed for power electronic applications will be introduced. Emphasis will be placed on SiC MOSFETs, which are currently being inserted in the majority of SiC based power electronic systems. Aspects of device fabrication will be given, with stress on processes that do not carry over from the mature Si manufacturing world and are thus specific to SiC. Finally, the presentation will highlight common SiC Edge Termination techniques, which allow devices to reach their full high-voltage potential.

12:10-12:55 The importance of the diffusion currents in the photoelectric investigations of the MIS system

Lecturer: Prof. Henryk M. Przewłocki, IEEE Senior Member, IEEE EDS Distinguished Lecturer, Instytut Technologii Elektronowej (ITE Warsaw), Poland

Abstract: The fundamental property of any nanoelectronic material or system is its energy band diagram, which allows to predict its physical properties, potential applications and/or limitations. The most effective methods of band diagram determination are the photoelectric methods, which deserve therefore detailed theoretical analysis, as well as precisely controlled experimental procedures. It is shown in this paper that the commonly accepted and currently applied theory (further called classical theory) of internal photoemission in the metal-insulator-semiconductor (MIS) system, which very well represents its experimental characteristics taken at high enough electric fields E, in the insulator, fails at low electric fields (usually for E < (104-105) V/cm), i.e. in the vicinity of the point where the photocurrent changes sign (I=0). This failure of the classical theory will be demonstrated by comparing the characteristics calculated using the classical theory with the experimental characteristics taken in the range of low electric fields in the insulator. It was already shown some time ago, by the present author that this discrepancy results from the neglect of the diffusion currents, which become important at low electric fields in the insulator. In this paper the origin, the magnitude and the role of diffusion current in determination of the MIS system photoelectric characteristics at low electric fields in the insulator will be quantitatively analyzed. The theory of the photocurrent vs. gate voltage characteristics, at different wavelengths of light illuminating the structure under test, with diffusion currents taken into account will be presented. It will be shown that characteristics calculated using this theory remain in good agreement with the relevant experimental characteristics. The ability to accurately predict these characteristics in the range of low electric fields opens the possibilities of developing new measurement methods of the MIS system crucial parameters. Examples of such methods will be demonstrated.

13:05-14:05 Lunch Break

14:05-14:50 Verilog-A compact modelling of SiC devices with Qucs-S, QucsStudio and MAPP/Octave FOSS tools

Lecturer: Prof. Mike Brinson, Fellow of the IET, CEng., Member of the Institute of Physics, CPhys. Centre for Communications Technology, London Metropolitan University, UK

Abstract: The purpose of this presentation is provide an overview of the fundamentals of the Verilog-A hardware description language and its use in compact modelling of established and emerging semiconductor technology devices. With the adoption of Verilog-A as the standardised model interchange language by CMC, a knowledge of this subject is of increasing importance to the modelling community. Similarly, access to freely available Verilog-A modelling tools and circuit simulators is essential if Verilog-A modelling techniques are to be widely adopted. For this reason, in an attempt to encouraging all who attend to experiment with Verilog-A. the presentation is based on the Qucs-S, QucsStudio and the MAPP/Octave FOSS software. Throughout the talk a series of modelling case studies outline the stages in the development of Verilog-A models for established and SiC semiconductor devices. In the later stages of the presentation participants are also introduced to using the Berkeley MAPP tools with Qucs-S/Xyce.

15:00-15:45 FOSS TCAD/EDA Tools for Advanced Compact Modeling

Lecturer: Dr. Wladek Grabinski, IEEE Senior Member, IEEE EDS Distinguished Lecturer, MOS-AK (EU), Switzerland

Abstract: Compact/SPICE models of circuit elements (passive, active, MEMS, RF) are essential to enable advanced IC design using nanoscaled semiconductor technologies. Compact/SPICE models are also a communication means between the semiconductor foundries and the IC design teams to share and exchange all engineering and design information. To explore all related interactions, we are discussing selected FOSS CAD tools along complete technology/design tool chain from nanascaled technology processes; thru the MOSFET, FDSOI, FinFET and TFET compact modeling; to advanced IC transistor level design support. New technology and device development will be illustrated by application examples of the FOSS TCAD tools: Cogenda TCAD and DEVSIM. Compact modeling will be highlighted by review topics related to its parameter extraction and standardization of the experimental and measurement data exchange formats. Finally, we will present two FOSS CAD simulation and design tools: ngspice and Qucs. Application and use of these tools for advanced IC design (e.g. analog/RF IC applications) directly depends the quality of the compact models implementations in these tools as well as reliability of extracted models and generated libraries/PDKs. Discussing new model implementation into the FOSS CAD tools (Gnucap, Xyce, ngspice and Qucs as well as others) we will also address an open question of the compact/SPICE model Verilog-A standardization. We hope that this presentation will be useful to all the researchers and engineers actively involved in the developing compact/SPICE models as well as designing the integrated circuits in particular at the transistor level and then trigger further discussion on the compact/SPICE model Verilog-A standardization and development supporting FOSS CAD tools.

15:55 End of MQ

[Special Issue] TED on “Compact Modeling for Circuit Design"

Call for papers for 

a Special Issue of IEEE TED

on

Compact Modeling for Circuit Design

Submission deadline: April 30, 2018               Publication date: January 2019

In order to capture the full potential of semiconductor devices, compact device models and design software are critically needed. Predictive and physical device and circuit design software are required to accelerate development cycles and tackle issues of device efficiency, manufacturing yield and product stability. The performance/accuracy of the design software is dependent on the availability of accurate device models, and for circuit design, compact models.

In particular, compact device models are the vehicle that allows the design of circuits using the targeted devices. The compact model should not only accurately capture the physics of the device in all operation regimes, but at the same time should also have an analytical or semi-analytical formulation to be used in automated design tools for the simulation of circuits containing several or many devices. On the other hand, compact models can also be used as a tool to make clear estimations and predictions of the performances of future devices following technological trends. The lack of adequate compact models for a number of emerging devices is mostly due to the insufficient understanding of the physical mechanisms that govern their behaviours. Regarding many emerging non-silicon structures, devices, circuit and system designers very often rely on empirical behavioural macro-models and/or use existing silicon device compact models based on the conventional understanding of transport processes. However, for these emerging non-silicon devices, neither approach provides a fully adequate device description under all operation conditions, nor the quantitative predictive quality required for the accurate production quality design.

Therefore, the main objective of this dedicated special issue is to engage Electron Devices Community in a serious discussion with their scholarly contributions specifically focused on solving major challenges in the broad area of compact device modeling for circuit design.

Suggested topics include but not limited to:

1. Silicon MOSFET modeling: Advanced Bulk MOSFETs; SOl MOSFETs; Multi-Gate MOSFETs: Double-Gate MOSFETs, Surrounding-Gate MOSFETs, FinFETs, UTB SOI MOSFETs; Junctionless MuGFETs; Power and High Voltage MOSFETs.
2. Junction-based and compound semiconductor FET modeling: Advanced MESFETs; Advanced HEMTs; lIl-V and Ill-N; MOSFETs; Advanced IFETs.
3. Diode and bipolar transistor modeling: Advanced BJTs; HBTs; IGBTs; pn and pin diodes; Varactors.
4. Emerging transistor modeling: Tunnel FETs; Molecular transistors; Single Electron Transistors; Quantum Dot Transistors; Negative Capacitance Transistors.
5. Emerging semiconductor devices: Memories, MRAM, PCRAM etc.; Spintronic devices; Layered/2D materials
6. Thin-Film FETS (TFT): a-Si:H TFTs; Polycrystalline Si TFTs; OTFTs and OECTs; Oxide TFTs; Single-crystal TFTs.
7. Modeling of physical effects: Noise; High frequency operation; Mismatch; Strain; High energy particle interactions in ICs (Cosmic rays and energy beams); ESD events; Ballistic and quasi-ballistic transport; Layout dependent effects.
8. Photonic devices: LEDs and OLEDs; Photodiodes; Solar cells; Photodetectors; SPADs.
9. Model implementation in EDA tools and applications: Model code adaptation to EDA tools; Computational model performances in design tools; Challenges of model implementation in design tools; Compact model applications to variation and statistical analysis; Compact model applications to thermal analysis; Compact model applications to design exploration; Compact model applications to design optimization; Compact model applications to device process improvements; Compact modeling for BSD prediction; Circuit design using new compact models.

Submission instructions: Manuscripts should he submitted in a double column format using an IEEE style file Please visit the following link to download the templates:

http://www,ieeeiorg/publicationsistandards/publications/authors/author7templates,html

In your cover letter, please indicate that your submission is for this special issue. Please submit papers using the website: http://mc.manuscriDtcentral.com/ted

Guest Editors:

1. Benjamin Iniguez, URV, Tarragona (SP)
2. Yogesh Chauan, IIT Kanpur (IN) 
3. Andries Scholten, NXP Semiconductors, Eindhoven (NL)
4. Ananda Roy, Intel Corporation, Portland, OR (USA)
5. Slobodan Mijalkovic, Silvaco Europe Ltd, St. Ives (UK)
6. Sadayuki Yoshitomi, Toshiba Corporation, Tokyo (J)
7. Kejun Xia, NXP Semiconductors, Phoenix, AZ (USA) 
8. Wladek Grabinski, GMC Consulting, Commugny (CH) 
9. Kaikai Xu, UEST of China, Chengdu (CN) 

SSCS Members Who Are 2017 IEEE Fellows

SSCS members who are IEEE Fellows pose with SSCS President, Jan Van der Spiegel and IEEE President, Karen Bartelson at ISSCC 2017. From left to right- Jan Van der Spiegel, Zhihua Wang, Andrei Vladimirescu, Carlo Samori, Borivoje Nikolic, Junichi Nakamura, Deog-kyoon Jeong, Hideto Hidaka, Payam Heydari, Edoardo Charbon, and Karen Bartleson 

Mini-Colloquium (MQ) on Nanoelectronics

AGENDA
DATE: Saturday Aug. 26, 2016

VENUE: IIT Kanpur L16

This Mini-Colloquium (MQ) on Nanoelectronics is being hosted by the IEEE Electron Device Society UP Chapter in collaboration with the Department of Electrical Engineering at IIT Kanpur. Distinguished speakers from renowned universities will be presenting on wide range of topics in Nanoelectronics. The MQ will be organized into 1 hour talks by the speakers. The agenda would be as follows:

Time	Topic	Speaker
9:00 - 9:15	Inauguration
9:15 - 9:30	High Tea
9:30 - 10:30	Nanotransistors with 2D materials: Opportunities and Challenges	Prof. Navkanta Bhat IISc
10:30 - 11:30	Revisiting gate C-V characterization for high mobility semiconductor MOS devices	Prof. Anisul Haque East West Univ.
11:30 - 11:45	Tea
11:45 - 12:45		Prof. V. Ramgopal Rao IIT Delhi
12:45 - 14:15	Lunch
14:15 - 15:15	ASM-HEMT - First Industry Standard Compact Model for GaN HEMTs	Prof. Yogesh Singh Chauhan IIT Kanpur
15:15 - 16:15	Spintronics - Perspectives and Challenges	Prof. Brajesh Kumar Kaushik IIT Roorkee
16:15 - 16:30	Tea
16:30 - 17:30	Advanced Hetero structure based Nano Scale MOSFETs	Prof. Chandan Kumar Sarkar Jadavpur Univ.

Coordinator: Dr. Yogesh S.Chauhan IIT Kanpur, India
Website: http://www.iitk.ac.in/nanolab/MQ/index.html

2017 IEEE Andrew S. Grove Award

Prof. Sorin Cristoloveanu,  CNRS at IMEP-LAHC

2017 IEEE Andrew S. Grove Award Recipient

“For contributions to silicon-on-insulator technology and thin body devices”

A visionary device physics researcher, Sorin Cristoloveanu saw the potential that silicon-on-insulator (SOI) technology held for the semiconductor industry in producing competitive microelectronics components with improved performance when others considered it a niche field. As early as 1976, he discovered key mechanisms of thin-body devices that have led to the development of transistors from the simplest (zero gate) to the most complicated (four gates). Among several concepts unveiled by his group, the demonstration during the 1980s that volume inversion occurs in all nano-body devices was revolutionary at the time and helped drive research that led to double-gate transistors and today’s tri-gate FinFET devices. His Pseudo-MOSFET method developed in 1992 has become an industry standard for wafer monitoring without having to actually fabricate devices. More recently, Cristoloveanu’s SOI expertise has led to innovative devices for low-power memory and sharp-switching circuits. An IEEE Fellow, Cristoloveanu is the director of research at CNRS at IMEP-LAHC, Grenoble, France [read more...]

IEEE Workshop on Compact Modeling

IEEE Workshop on Compact Modeling

March 3, 2017

Technical Sponsorship by: IEEE Electron Devices Society UP Chapter

Organized by: Department of Electrical Engineering, IIT Kanpur

Coordinator: Prof. Yogesh Singh Chauhan

Venue: Outreach Auditorium, IIT Kanpur

IEEE Workshop on Compact Modeling Agenda:

Time	Topic	Speaker
8:00 - 8:15	Workshop inauguration by Director IIT Kanpur and IEEE-UP Chairman
8:15 - 9:00	Industry Standard Compact Modelling	Dr. Yogesh Singh Chauhan IIT Kanpur
9:00 - 9:30	Modelling of mismatch and process variations	Dr. Abhisek Dixit IIT-Delhi
9:30 - 10:00	TBA	Dr. Nihar Ranjan Mohapatra IIT-Gandhinagar
10:00 - 10:30	Modelling of normally-off GaN based MOSHEMT	Dr. Trupti Ranjan Lenka NIT Silchar
10:30 - 10:45	ASM-HEMT: Industry standard compact model for GaN HEMTs	Dr. Sudip Ghosh IIT-Kanpur
10:45 - 11:00	Modelling of quasi ballistic transport in nano-wire transistors	Mr. Avirup Dasgupta IIT Kanpur
11:00 - 11:15	TBA	Mr. Priyank Rastogi IIT Kanpur
11:15 - 11:30	Compact modelling of TMD based thin body transistors	Mr. Chandan Yadav IIT Kanpur
11:30 - 11:45	Tea Break
11:45 - 12:15	Qualification techniques for sim models for EEsof products	Mr. Mohit Khanna Keysight Technologies
12:15 - 12:45	High frequency device characterization and modeling for THz applications	Prof. Thomas Zimmer IMS-BORDEAUX
12:45 - 2:00	Lunch
2:00 - 2:30	Device design consideration: IoT perspective	Dr. Santosh Kumar Vishvakarma IIT-Indore
2:30 - 3:00	TBA	Dr. Aditya Sankar Medury IISER-Bhopal
3:00 - 3:30	Simulations, analysis and applications of doping- and junction- free transistors	Dr. Jawar Singh IIIT-Jabalpur
3:30 - 4:00	Design of radiation hardened 24-bit ADC for generic applications	Mr. H.S.Jattana SCL
4:00 - 4:15	Tea Break
4:15 - 4:45	Role of Feynman diagrams in energy band structure of materials - A post density functional theory approach	Dr. Sitangshu Bhattacharya IIIT-Allahabad
4:45 - 5:15	TBA	Dr. Swaroop Ganguly IIT-Bombay
5:15 - 5:45	TBA	Dr. Saurabh Lodha IIT-Bombay
5:45 - 6:15	TBA	Dr. Udayan Ganguly IIT-Bombay
6:15 - 6:45	TBA	Dr. Manoj Saxena Delhi University
6:45 - 7:00	Closing Keynote

3rd Training Course on Compact Modeling

 3rd TCCM, 

 organized as IEEE EDS Mini-Colloquium 
 (http://eds.ieee.org/lectures.html?eid=136)

Co-organizer: Institute of Electron Technology, Warsaw, Poland
Technical Program Promoter: DMCS, Lodz University of Technology, Łódź, Poland

Date: June 24, 2015.
Place: Hotel Bulwar (Lejda room) ul. Bulwar Filadelfijski 18, 87-100 Toruń, Poland
www: http://www.hotelbulwar.pl

Final schedule of TCCM:
9:00 Wladek Grabinski, Opening
9:10 Henryk Przewłocki, "Weaknesses and corrections of the classical theory of photoelectric phenomena in the MOS system"
10:00 Juin J.Liou, "Compact Modeling of Junction Failure in Semiconductor Devices Subject to Electrostatic Discharge Stresses"
10:50 Coffee break
11:10 Jean-Michel Sallese, "Modeling Junctionless Field Effect Transistors"
12:00 Mike Brinson, "A unified approach to compact device modelling with the open source packages Qucs/ADMS and MAPP/Octave"
13:00 Lunch
14:30 Benjamin Iniguez, "Physically-Based Compact Modeling of GaN HEMT"
15:20 Wladek Grabinski, "Verilog-A Compact Model Standardization"
16:10 Daniel Tomaszewski, "Compact modeling and statistical modeling for parametric yield improvement"
17:00 Wladek Grabinski, Closing

IEEE Swiss CAS/ED Workshop 2014 on Memristive Devices and Neuromorphic Applications

 IEEE Swiss CAS/ED Workshop 2014 on Memristive Devices and Neuromorphic Applications 

 (http://www.ieee.ch/chapters/cas-ed/cas-ed-news/2014-11-27/) 

Date: Friday 28 Nov, 2014
Time: 10:00-19:00
Place: UZH, Irchel Campus, Room Y35 F51 (morning session) Y10 03/04 (afternoon session), Building 55 Foyer (apero). Closest tram stop is Tram 9/10 at Irchel. See here for University of Zurich map.

At this one day workshop, experts in Memristive Devices and Neuromorphic Applications will present their recent advances in Circuits and Systems and Electron Devices. The workshop includes a demo and poster session, and a concluding apero.

Resistive memory devices also known as "memristors" are being actively researched to address the widening gap in performance between storage and the rest of the computing system. There is also a potential for such devices to serve simultaneously as both memory and logic, or even as components of a neuromorphic computing hardware based on brain architecture. The investigation of the use of these devices in a host of applications in science and technology are currently being explored. Swiss developers are very active in these fields and the area of neuromorphic computing. This one-day IEEE workshop brings them together with potential research and development partners and end users in industry and academia.

The presentations will cover a range of topics focus on memristive technology and possible computing applications. A poster session including demonstrations of relevant technologies will also be offered.

All presentations will be in English.

Registration: Registration is open to the public but is mandatory. There will be a registration fee which includes lunch and apero. Please register at www.iniforum.ch/casedws14/registration.php.

Registration will be closed by 14.11.2014 or when the maximum number of places is reached. Registration must be cancelled by 21.11.2014 for refund.

Posters and Demos registration: We invite demos and posters. Poster or demo presentations must also register for the workshop (see above). Posters or demos must be registered so that we can plan space for them. Please use this demo and registration form to register.

EDS VLSI Technology and Circuits TC Report

 EDS VLSI Technology and Circuits Technical Committee Report

 http://eds.ieee.org/eds-newsletters.html

The VLSI Technology and Circuits Technical Committee was formed in 1998 under the leadership of Professor Charles G. Sodini (MIT) and followed by Dr. H.-S. Philip Wong (IBM), Werner Weber (Infineon), Dr. James A. Hutchby (SRC) and Dr. Bin Zhao (Freescale Semiconductor). Since its formation, the VLSI Committee has made it their mission to identify new technical trends, help foster new technical concepts, and serve the emerging needs of the Electron Devices and Solid-State Circuits communities in VLSI. The committee members include many well recognized technical experts representing a very wide spectrum of technical expertise in VLSI devices, technology, and circuits. Every year the committee brainstorms (by email), ideas that are suitable for new workshops, special issues for a journals, panel sessions, and special sessions for conferences. Committee members then drive these ideas forward and find a way to make them happen; either by being the organizers themselves, or by finding suitable organizers for the topic. They work closely together with journal editors and conference organizers. It is much easier to attach new workshops to existing conferences, than to establish new conferences. 

[read more at http://eds.ieee.org/eds-newsletters.html]

IEEE TED Call for Papers: Variation aware technology and circuit codesign

 Call for papers for a special issue of 

 IEEE Transactions on Electron Devices 

"Variation aware technology and circuit codesign" 

The special issue on "variation aware technology and circuit co design is devoted to the research and development activities on variation aware process device technology and co-optimization with circuit design. Rapid pace of new technology introduction to CMOS technology requires much more sophisticate optimization of process, device, and circuit design, in order to maximize return on investment. Careful optimization of process technology, device structure, layout and circuit design in holistic manner enables significant performance improvement while reducing overall power consumption with least amount of area penalty.

Among many challenges for this holistic optimization, higher process and device variation becomes one of most critical issues as process technology is marching into below 20nm node.

New material technology and non-planar device structure add additional variation source on top of conventional geometrical effect. Not only reducing extrinsic portion of variation is important understanding the effect of such variation in various actual circuit design is also very important In addition to addressing variation at individual process and design element, this special edition also touches on the impact of variation aware optimization to overall SOC design that requires both high performance and low power functional blocks.

This special edition includes, but not limited to, following topics:

• Variation reduction methods of advanced process technology, including patterning, deposition and etch processes
• Variation reduction methods of dvanced device technology, including FinFET, Nanowire, FDSOL etc.
• Co-optimization of technology and circuit to minimize variation and/orimpact of variation.
• ТCAD to understand the source of variation and provide practical method to improve.
• Novel process and device technology to cope with variation issue in coming nodes.
• SOC integration and design methodology to take process device variation into account.

Please submit papers by using the website: https://mc.manuscriptcentral.com/ted link here

BE SURE TO MENTION THE SPECIAL ISSUE WITHIN THE COVER LETTER

Submission Deadline: October 31, 2014
Scheduled Publication Date: June 2015

Guest Editors:
Stanley S.C. Song Qualcomm
Huiling Shang, IBM
Каustav Banerjee, University of California, Santa Barbara
Shuji Ikeda, TEI solution

If you have any questions about submitting a manuscript, please contact:
Jo Ann Marsh (j.marsh@ieee.org) T-ED Special Issues Administrative Support

Dr. Jindal has been nominated for the Delegate-Elect/Director-Elect 2015

Dr. Renuka Jindal is Professor of Electrical and Computer Engineering at the University of Louisiana at Lafayette, LA, USA since 2002. His research and teaching interests lie in the theory and practice of random processes applicable to a wide variety of phenomena in electronic and photonic devices and circuits, lightwave and wireless communications systems and biological organs. Dr. Jindal was elected Fellow of IEEE in 1991 for his seminal work reducing MOSFET noise by almost an order of magnitude for analog and RF applications. He is also a recipient of the IEEE 3rd Millennium medal. For last four decades of his dual career in industry and academia, Dr. Jindal rose through the ranks as Editor, Editor-in-Chief, VP of Publications, and as EDS President in 2010- 2011. As President he formulated the vision and mission of EDS enhancing member benefits launching a plethora of initiatives reversing the decline in EDS membership. A partial list of his accomplishments is given below:

• Brought together 6 societies and 1 council to launch highly successful IEEE Journal of Photovoltaics mushrooming IEEE’s share in the PV space http://ieeexplore.ieee.org/stamp/stamp.jsp?tp=&arnumber=6055242
• Launched EDS webinar series serving the practicing engineers; now considered a best practice in IEEE http://eds.ieee.org/webinars.html
• Launched the 1st EDS OPEN ACCESS Journal J-EDS http://ieeexplore.ieee.org/stamp/stamp.jsp?tp=&arnumber=6471856
• Founded QuestEDS for members to get authoritative answers to technical questions within 2 weeks http://eds.ieee.org/questeds/why-questeds.html
• Founded the EDS Celebrated Member program to honor EDS Nobel Laureates and other luminaries. http://eds.ieee.org/celebrated-members.html
• Mentored the launch of a high-school outreach program (EDS-ETC) across United States and abroad http://eds.ieee.org/the-eds-etc-program.html
• As chapter partner, for over 15 years, stimulated a spectacular growth of EDS chapters in South Asia from one to 19 serving Division I.

As Senior-Past President of EDS Dr. Jindal is still very much engaged with IEEE. Recently, Dr. Jindal has been nominated by IEEE Division I to run for the Delegate-Elect/Director-Elect 2015 position in the upcoming IEEE elections. The electorate consists of members of three societies i.e. Electron Devices (ED), Solid-State Circuits (SSC) and Circuits and Systems (CAS). The slate consists of three candidates one from each of these societies. 

On his behalf, I suggest to contact your colleagues in IEEE regions 1-10 for his support since IEEE ballots will be out by August 15.

CTFT 2012

4th International Workshop on Compact Thin-Film Transistor (TFT) Modeling for Circuit Simulation

This workshop will provide a forum for discussions and current practices on compact TFT modeling. The workshop is sponsored by IEEE EDS Compact Modeling Technical Committee in joint collaboration with Cambridge University. A partial list of the areas of interest includes:

• Physics of TFTs and operating principles
• Compact TFT device models for circuit simulation
• Model implementation and circuit analysis techniques
• Model parameter extraction techniques
• Applications of compact TFT models in emerging products
• Compact models for interconnects in active matrix flat panels

The workshop organizers:
Department of Engineering, University of Cambridge, Cambridge, UK
Technical School of Engineering, University Rovira i Virgili, Tarragona, Spain