[paper] Characterization and Modeling of SOI LBJTs at 4K

Yuanke Zhang, Yuefeng Chen, Yifang Zhang, Jun Xu, Chao Luo, and Guoping Guo

Characterization and Modeling of Silicon-on-Insulator 

Lateral Bipolar Junction Transistors at Liquid Helium Temperature

IEEE TED Vol. XX, No. XX, preprint arXiv:2309.09257 (2023).

University of Science and Technology of China (USTC), Hefei 230026, Anhui, China

CAS Key Lab ofQuantum Information, Hefei 230026, Anhui, China.

Abstract: Conventional silicon bipolars are not suitable for low-temperature operation due to the deterioration of current gain (β). In this paper, we characterize lateral bipolar junction transistors (LBJTs) fabricated on silicon-on insulator (SOI) wafers down to liquid helium temperature (4 K). The positive SOI substrate bias could greatly increase the collector current and have a negligible effect on the base current, which significantly alleviates β degradation at low temperatures. We present a physical-based compact LBJT model for 4 K simulation, in which the collector current (IC) consists of the tunneling current and the additional current component near the buried oxide (BOX)/silicon interface caused by the substrate modulation effect. This model is able to fit the Gummel characteristics of LBJTs very well and has promising applications in amplifier circuits simulation for silicon-based qubits signals.

Fig: IC (solid lines) and IB (dash lines) versus VBE of LBJT at different temperatures 

under (a) VBOX = 0 V; (b) VBOX = 12 V, VCE = 1 V.

Acknowledgement: The device fabrication was done by Prof. Zhen Zhang’s group in the Angstrom Microstructure Laboratory (MSL) at Uppsala University. Dr. Qitao Hu, Dr. Si Chen, Prof. Zhen Zhang are acknowledged for the device design and fabrication, and the technical staff of MSL are acknowledged for their process support.

[book] Tunneling Field Effect Transistors

Tunneling Field Effect Transistors
Design, Modeling and Applications

Edited By T. S. Arun Samuel, Young Suh Song, Shubham Tayal, P. Vimala, Shiromani Balmukund Rahi

ISBN 9781032348766
1st Edition; 316 Pages; 15 Color & 232 B/W Illustrations
June 8, 2023 by CRC Press

Description: This book will give insight into emerging semiconductor devices from their applications in electronic circuits, which form the backbone of electronic equipment. It provides desired exposure to the ever-growing field of low-power electronic devices and their applications in nanoscale devices, memory design, and biosensing applications.

Tunneling Field Effect Transistors: Design, Modeling and Applications brings researchers and engineers from various disciplines of the VLSI domain to together tackle the emerging challenges in the field of nanoelectronics and applications of advanced low-power devices. The book begins by discussing the challenges of conventional CMOS technology from the perspective of low-power applications, and it also reviews the basic science and developments of subthreshold swing technology and recent advancements in the field. The authors discuss the impact of semiconductor materials and architecture designs on TFET devices and the performance and usage of FET devices in various domains such as nanoelectronics, Memory Devices, and biosensing applications. They also cover a variety of FET devices, such as MOSFETs and TFETs, with various structures based on the tunneling transport phenomenon.

The contents of the book have been designed and arranged in such a way that Electrical Engineering students, researchers in the field of nanodevices and device-circuit codesign, as well as industry professionals working in the domain of semiconductor devices, will find the material useful and easy to follow.

Table of Contents:

Chapter 1. Challenges of Conventional Cmos Technology in Perspective of Low Power Applications

Chapter 2. Basic Science and Development of Subthreshold Swing Technology

Chapter 3. Historical Development of MOS technology to Tunnel FETs

Chapter 4. Modeling of Gate Engineered TFETs: Challenges and Opportunities

Chapter 5. Modeling of Gate Engineered TFET: challenges and Opportunities.

Chapter 6. Evolution of Heterojunction Tunnel Field Effect Transistor and its Advantages

Chapter 7. Analog / RF performance analysis of TFET device

Chapter 8. DC Analysis and Analog/HF Performances of GAA-TFET with Dielectric Pocket

Chapter 9. Investigation on Ambipolar Current Suppression in Tunnel FETs

Chapter 10. Analysis of Channel Doping Variation on Transfer Characteristics to High Frequency performance of F-TFET

Chapter 11. Design of Nanotube TFET Biosensor

Chapter 12. TFET-based Memory Cell Design with Top-down Approach

Chapter 13. Designing of nonvolatile memories utilizing Tunnel Field Effect Transistor

Chapter 14. TFET-based Universal

Chapter 15. TFET-based Level Shifter Circuits for Low Power Applications

[paper] Model for Ultra-Scaled MoS2 MOSFET

Weiran Cai, Wenrui Lan, Zichao Ma*, Lining Zhang, Mansun Chan*

A Full-region Model for Ultra-Scaled MoS2 MOSFET Covering Direct Source-Drain Tunneling 

9th International Symposium on Next Generation Electronics (ISNE), 2021, pp. 1-3,

DOI: 10.1109/ISNE48910.2021.9493621

College of Electronic and Information Technology, Shenzhen University, Shenzhen, China

* Hong Kong University of Science and Technology, Hong Kong, China

Abstract: A full-region model for ultra-scaled monolayer MoS2 MOSFETs is reported in this work. The electrostatic potential in the scaled transistor structure is analyzed based on a first-principle verified potential model. A continuous full region current model is then developed to capture the short channel effects. Based on the potential model, the barrier height and width for direct source-drain tunneling are obtained. The direct tunneling module reproduces the essential physics observed from numerical device simulations. After integration with the thermionic emission model, the full-region current model is implemented into a SPICE simulator and the model convergence is verified by simulating typical circuits.

A drift-diffusion current model of the full region is straightforwardly derived with Taylor expansions of a Si model or from the Pao-Sah integral. It resembles the EKV current model and allows similar expressions of small signal models:

Fig: The impact of SCEs on devices of different channel length is showed in (a) Ids–Vg and (b) Ids–Vd characteristics predicted by the model covering SCEs. When channel length becomes smaller, SCEs becomes more serious. 

Acknowledgement: This work is supported in part by the Natural Science Foundation of China under Grant 61704144, the Shenzhen Science and Technology Project under JCYJ20180305125340386, the General Research Fund (GRF) from Research Grant Council (RGC) of Hong Kong under Grant 16206219

[paper] Effect of the AC-Signal Frequency on Flat-Band Voltage of Al/HfO2/SiO2/Si Structures

Andrzej Mazurak, Bogdan Majkusiak

Investigation of the Anomalous Effect of the AC-Signal Frequency 

on Flat-Band Voltage of Al/HfO2/SiO2/Si Structures

Solid-State Electronics (2021) SSE 108107 

DOI:10.1016/j.sse.2021.108107

*TU Warsaw, Institute of Microelectronics and Optoelectronics, Koszykowa 75, 00-662 Warsaw, Poland

Abstract: MIS structures with double-layer HfO2/SiO2 gate stacks were fabricated. The admittance measurements revealed an anomalous voltage shift of the capacitance-voltage characteristics, modulated by the ac signal frequency. The effect is discussed in terms of the oxide charge modulation through the frequency dependent leakage mechanism.

Fig: Measured Gpm conductance–voltage characteristics for the n-type MIS structure.

• An anomalous effect of the ac-signal frequency on the voltage shift of the CV characteristics of Al/HfO2/SiO2/Si devices was observed.
• The observed effect is stable, reproducible, and reversible and is not driven by the measurement procedure or the measurement protocol parameters.
• The effect is explained through a frequency dependent leakage conductance which affects the electric charge trapped interior the gate stack.
• A linear dependence of the leakage conductance on the ac signal frequency is observed.

[paper] Simulations of transient processes in the nc-MOS structures

D. Tanous, A. Mazurak and B. Majkusiak 

Simulations of transient processes and characteristics of the nc-MOS structures 

Microelectronic Engineering, 

Volume 178, 2017, pp/ 173-177, 

DOI: 10.1016/j.mee.2017.05.013 

Abstract: Experimentally measured capacitance-voltage and current-voltage characteristics of the metal-insulator-semiconductor structures with nanocrystals embedded in the insulator often exhibit formations which result from charging/discharging processes of the nanocrystals and are difficult to explain and predict intuitively. Time dependent simulations as presented in this paper can be helpful in their analysis. The paper presents a study of the impact of selected geometrical parameters on their characteristics with the bias voltage ramp rate as a parameter.

FIG: a.) nc-MIS Structure; b.) Bias voltage ramp stimulation; c.)  CV and IV Simulations results

[paper] On the Physical Behavior of Cryogenic IV and III-V Schottky Barrier MOSFET Devices

On the Physical Behavior of Cryogenic IV and III–V Schottky Barrier MOSFET Devices

Mike Schwarz, Member, IEEE, Laurie E. Calvet, Member, IEEE, John P. Snyder, Member, IEEE, Tillmann Krauss, Udo Schwalke, Senior Member, IEEE, and Alexander Kloes, Senior Member, IEEE

in IEEE TED , vol.PP, no.99, pp.1-8

doi: 10.1109/TED.2017.2726899

Abstract: The physical influence of temperature down to the cryogenic regime is analyzed in a comprehensive study and the comparison of IV and III-V Schottky barrier (SB) double-gate MOSFETs. The exploration is done using the Synopsys TCAD Sentaurus device simulator and first benchmarked with experimental data. The important device physics of both SB-MOSFETs and conventional MOSFETs are reviewed. The impact of temperature on device performance down to the liquid-nitrogen regime is then explored. We find reduced drive currents in SB-MOSFETs fabricated on small effective mass materials and that SB lowering can significantly improve SB-MOSFETs, especially at low temperatures [read more...]

This article has been accepted for inclusion in a future issue of this journal. Content is final as presented, with the exception of pagination

TED Call for Papers on Compact Modeling of Emerging Devices

Compact Models (CMs) for circuit simulation have been at the heart of CAD tools for circuit design for almost five decades. As the mainstream CMOS technology is scaled into the nanometer regime, development of a truly physical and predictive CM for circuit simulation that covers geometry, bias, temperature, DC, AC, RF, and noise characteristics becomes a major challenge. The last call for a special issue on “advanced compact models and 45-nm modeling challenges” was in 2005. Seven years have passed, new technology nodes have been implemented, compact models have evolved and new compact models as well as compact models for new devices are being developed. Therefore, there is a need for another special issue dedicated to the advancement and challenges in core field-effect transistor (FET) models for 32-nm technologies and beyond as well as emerging technologies. For the core FET models, the associated noise/mismatch and reliability/variability models as well as proximity effects have become an essential part of the modeling effort. High-frequency, high-voltage, high-power, high-temperature devices have been extensively investigated, and their CMs are being reported in the literature. Device/circuit interaction and layout-dependent proximity effects are also hot topics today that are essential in nanometer chip designs. It is timely to report advances in these CMs in the 32-nm/22-nm technology era.

Concurrently, nonclassical MOSFETs as well as their CMs, such as multigate FinFETs and nanowire FETs, partially/fully-depleted ultrathin body (UTB) SOT, and thin-film transistors (TFTs), have emerged over the past decades. With the announcement of FinFETs being used in 22-nm and sub-22nm technology nodes, the need for such core models for fabless designers becomes an urgent reality. In these nonclassical devices, transistors are essentially short-channel, narrow-width, and thin-body. Tt is also an interesting topic to discuss and debate on the two different formalisms “top-down” drift-diffusion formulation adding ballistic effects versus “bottom-up” quasi-ballistic formulation adding scattering effects for modeling the real devices that are somewhere in between. Heterogeneous integration of various devices into the CMOS platform also becomes an important trend.

In addition, it is also timely to report advances in CMs of emerging devices beyond traditional silicon CMOS, such as different materials (III-V/Ge channel, organic) and different source/drain injection mechanisms (Schottky-barrier, tunneling, and junctionless FETs). These emerging device options for future VLSI building blocks have been studied extensively, while good physical CMs are still lacking. The special issue in these topics will stimulate research and development to promote modeling efforts such that theory would lead and guide technology realization and selection for future generations.

The special issue for the TRANSACTIONS ON ELECTRON DEVICES on compact modeling of emerging devices is devoted to the review and report of advancements in CMs for 32-nm technologies and beyond, including bulk and nonclassical CMOS and their associated noise/mismatch and reliability/variability models, as well as various emerging devices as future generation device options. It is timely as the industry is in the transition from traditional planar bulk-CMOS towards vertical FinFET technologies, and exploration of heterogeneous integration with various materials and structural choices.

Please submit manuscripts by using the following URL: http://mc.manuscriptcentral.com/ted

MAKE SURE TO MENTION THE SPECIAL ISSUE IN THE COVER LETTER

Paper submission Deadline: June 30, 2013

Scheduled Publication Date: February 2014

Guest Editors:

Xing Zhou, Nanyang Technological University, 

Jamal Deen, McMaster University, 

Benjamin Iniguez, Universitat Rovira i Virgili, 

Christian Enz, Swiss Federal Institute of Technology, 

Rafael Rios, Intel Corp.

If you have any questions about submitting a manuscript, please contact:

Jo Ann Marsh 

IEEE EDS Publications Office

445 Hoes Lane Piscataway JN 08854

Phone: +1 732 562 6855

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Digital Object Identifier 10.1109/TED.2013.2253418

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