Showing posts with label Diode. Show all posts
Showing posts with label Diode. Show all posts

Aug 25, 2026

[paper] Datasheet‑Driven Automated Device Modeling

Siddharth Mohan, Mike Engelhardt, Tim McCune, and Jeff Strang
Datasheet-Driven Automated Device Modeling
22nd IEEE SMACD (2026) Dresden, Germany
DOI: 10.1109/SMACD70206.2026.11647759

* Qorvo Inc., CA, USA

Abstract: Accurate device models are a prerequisite fortrustworthy SPICE simulations, yet generating compact models from vendor datasheets has traditionally been time‑consuming anderror‑prone. QSPICE adds a Model Generators that build MOSFET, JFET, and diode models from commonly available datasheet values in minutes, integrating directly with its mixed‑mode simulator. We formalize a datasheet‑drivenworkflow (digitization, automated parameter mapping, simulation), and report qualitative validation across ID–VDS, ID–VGS, Coss, Qg, and IS–VSD characteristics using overlays from an industrial case study. We discuss adoption guidance, limitations, and opportunities for further quantitative benchmarking.

Fig: Automated model-generation workflow diagram.

AOB414 datasheet Available: https://www.designing-electronics.com/the-qspice-model-generator/


Mar 2, 2018

[paper] Compact modeling of SiC Schottky barrier diode and its extension to junction barrier Schottky diode

Dondee Navarro1, Fernando Herrera1, Hiroshi Zenitani2, Mitiko Miura-Mattausch1, Naoto Yorino2, Hans Jürgen Mattausch1,2, Mamoru Takusagawa3, Jun Kobayashi3 and Masafumi Hara3

Published 19 February 2018 • © 2018 The Japan Society of Applied Physics
Japanese Journal of Applied Physics, Volume 57, Number 4S

1 HiSIM Research Center, Hiroshima University, Hiroshima 739-8530, Japan
2 Graduate School of Engineering, Hiroshima University, Hiroshima 739-8530, Japan
3 Toyota Motor Corporation, Toyota, Aichi 470-0309, Japan

Abstract: A compact model applicable for both Schottky barrier diode (SBD) and junction barrier Schottky diode (JBS) structures is developed. The SBD model considers the current due to thermionic emission in the metal/semiconductor junction together with the resistance of the lightly doped drift layer. Extension of the SBD model to JBS is accomplished by modeling the distributed resistance induced by the p+ implant developed for minimizing the leakage current at reverse bias. Only the geometrical features of the p+ implant are necessary to model the distributed resistance. Reproduction of 4H-SiC SBD and JBS current–voltage characteristics with the developed compact model are validated against two-dimensional (2D) device-simulation results as well as measurements at different temperatures [read more: https://doi.org/10.7567/JJAP.57.04FR03]

Fig.: Electron current density in a JBS cross-section. JBS has a peak density at the n− region adjacent to the p+ implant.