First OpenSUSI MPW

1st OpenSUSI MPW Typeout

Junichi Okamura, Representative Director of OpenSUSI

In October 2025, OpenSUSI, in collaboration with Tokai Rika Co., Ltd., announced the disclosure of PDK information related to the company's 1μm CMOS process. Subsequently, created an environment for open source PDK in OpenSUSI's GitHub repository [1], and launched the open-source semiconductor manufacturing shuttle service "OpenSUSI-MPW" through OpenSUSI's website [1].

For this first OpenSUSI-MPW, by the application deadline on September 18, we received a total of 49 applications from companies, schools, and individuals, exceeding expectations. Users are not limited to individual designers; multiple private companies also use it as a practical tool for developing semiconductor design talent within their in-house structures. In addition, we received two applications for two slots from DX High Schools (key semiconductor schools), as well as many applications from several technical colleges and universities to utilize these slots in semiconductor design education. The manufactured chips are scheduled to be delivered to users around February 2027.

The main goal of OpenSUSI-MPW is not only to establish an open PDK and design environment, but also to provide an environment where everyone can experience manufacturing semiconductors they actually design and actually handling them as actual chips. This first session was the first achievement in which the environment was actually utilized by a diverse range of users, from high schools to companies.

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REF:
[1] https://github.com/OpenSUSI/TR-1um
[2] https://www.opensusi.org/mpw-service
[3] YouTube Channel "Ichiken / ICHIKEN": https://www.youtube.com/c/ICHIKEN-video
[4] Recent Invited OpenSUSI Conference Presentation 

IEEE ICTA Special OpenPDK Session; October 22, 2026, Singapore

Contact Information:

General Incorporated Association OpenSUSI

Junichi Okamura (Representative Director)

[ICTA] Special OpenPDK Session

 

The EDS Distinguished Lecturer (DL) Program helps local chapters connect with internationally recognized experts, educators, and authors in the field of electron devices. Through this program, chapters can invite distinguished speakers to deliver high-quality technical lectures and share their knowledge with students, researchers, and industry professionals. The program supports IEEE EDS mission to promote its technical activities, encouraging active participation and IEEE EDS membership, and strengthening local EDS chapters around the world. By bringing leading experts directly to local communities, the DL Program helps foster professional development, knowledge exchange, networking, and greater engagement within the electron devices community.

Wladek Grabinski, IEEE EDS Distinguished Lecturer, visited Singapore recently, it was it was unique opportunity to meet local EDS chapters and the experts in the field of electron devices. 

Here with Yawei Li, Nanyang Assistant Professor at School of Electrical and Electronic Engineering, Nanyang Technological University, Singapore. Previously, Prof. Li was a Lecturer at ETH Zürich, where he worked with Prof. Luca Benini. Prof. Li research focuses on AI efficiency, aiming to accelerate computation, reduce memory footprint, and mitigate power consumption in AI systems. His R&D group research improves AI model efficiency, maps AI models onto targeted hardware, and designs AI hardware to serve AI models for vision, language, and robotic tasks (see: https://ofsoundof.github.io/)

Prof. Yeo Kiat Seng of the Singapore University of Technology and Design (SUTD), Singapore, and Tianjin University, China, officially opened the 9th IEEE International Conference on Integrated Circuits, Technologies and Applications (ICTA 2026), held in Singapore on October 21-23, 2026. The conference provided an international IEEE forum for researchers, engineers, students, and industry professionals to present and exchange the latest developments in integrated circuit design, semiconductor technologies, and emerging applications. It also encouraged collaboration across different disciplines to address the challenges of our rapidly changing technological society. During his opening remarks, Prof. Yeo highlighted the growing importance of the OpenPDK initiative and the increasing adoption of FOSS CAD/EDA tools for integrated circuit design. He emphasized the value of these open technologies for both academic research and industrial innovation, helping to make advanced IC design more accessible to a broader community. With the personal support of Prof. Yeo and the full endorsement of the ICTA Organizing Committee, the conference program included a Special OpenPDK Session, providing a dedicated platform to discuss recent progress, challenges, and opportunities in open-source design technologies and ecosystem development. The Special Session was coordinated by local Singapore Section RL07/EP21/ED15 Joint Chapter was open to all the IEEE EDS members.

Special Session “OpenPDK - Global FOSS Scholar Platform" Program

T_1	MOS-AK and Verilog-A Standard Model and OpenPDK Practice Wladek Grabinski, IEEE EDS DL, MOS-AK (EU) IHP OpenPDK (D)
T_2	Open-Source Ecosystem Updates and Semiconductor Design Development Programs in Japan Jun-ichi Okamura, AIST Solutions, OpenSUSI (J)
T_3	Open-Source EDA Meets Industrial IC Design Ehrenfried Seebacher, ams-OSRAM AG (A)
T_4	Building an Open-Source Process Platform, Empowering VLSI Innovation and Development Da Zhang Zhejiang University/CTO, Zhejiang Chuangxin Integrated Process Platform (CN)
T_5	From Silicon to Design: Intelligent Measurement and Modeling for DTCO Yutao Ma, VP of R&D, Primarius Technologies. Ltd. (CN)
T_6	Beyond Moore, Application-Driven IC Innovation International Cooperation Opportunities at NICE Alex Gu, National Innovation Center Par Excellence (NICE) (CN)
T_7	2.5D/3D IC: AI+EDA Reshaping the System-Design-Technology Co-Optimization (STCO) Paradigm for Advanced Packaging Alex Zhao, Founder/CEO Zhuhai SiChip Technology Co., Ltd. (CN)
T_8	Modelling of semiconductor devices: the heart of innovation bridging academia and industrial applications Fujiang Lin, University of Science and Technology of China (USTC) (CN)

[MOS-AK] ESSERC W7 Workshop in Palma

Synopsys: The 23rd MOS-AK/ESSERC Compact Modeling Workshop in Palma de Mallorca brings together the international community advancing SPICE/Verilog-A modeling, OpenPDKs, and open-source IC design flows. Since 2002 ESSEDRC/ESSCIRC in Porto, MOS-AK has been the leading forum connecting technology developers, circuit designers, and FOSS CAD/EDA contributors, supporting knowledge exchange and strengthening the open semiconductor ecosystem. This year's program showcases cutting-edge developments: GaN MOS-HEMT compact models for emerging OpenPDKs, AI/ML-driven modeling workflows replacing manual tuning, cryogenic FD-SOI model libraries, fully open-source RFIC design case studies using IIC-OSIC-TOOLS, reliability insights for advanced CMOS and RF technologies, and a new OpenPDK MOSFET matching matrix IC enabling fast mismatch characterization. The workshop organizers are inviting engineers, researchers, and students who want a clear, practical view of modern device models and open simulation frameworks. It directly supports global OpenPDK adoption and aligns with European ODE4EC-AMS activities, promoting accessible, reproducible, and future-ready IC design methodologies.

9:30 - 11:00	W7 Workshop Opening
T_1	ODE4EC-AMS OpenPDK: the Status and Roadmap Wladek Grabinski IHP OpenPDK (D)
T_2	Advances in Open-Source Verilog-A Compilation and Simulatio> Arpad Buermen Uni. Ljubljana (SL)
T_3	Compact Modeling of GaN MOS-HEMTs for Open PDKs Ashkhen Yesayan EPFL (CH)
T_4	From Manual Tuning to Agentic AI: Transforming Device Modeling with AI/ML Roberto Tinti Keysight (US)
11:00 - 11:30	Coffee Break
T_5	Development of Cryogenic Model Libraries for FD-SOI Transistors Phanish Chava AdMOS (D)
T_6	Open-Source RFIC Design: Case Studies Using IIC-OSIC-TOOLS Georg Zachl JKU Linz (A)
T_7	Reliability topics for the miniaturization and qualification and OpenSilicon perspective Fernando Guarin IEEE EDS D1 (US)
P_1	[Poster] OpenPDK MOSFET Matching Matrix IC Juan Brito CEITEC (BR)
SSCS	Code-a-Chip Award Ceremony Akira Tsuchiya SSCS TC-OSE
13:00-14:00	End of the W7 Workshop and Lunch Break

The MOS-AK workshop was followed by ESSERC W2 Joint Workshop FAMES Pilot Line and SiNANO Institute reviwing the FDSOI Pilot Line Insights and Perspective. W2 was the first to present in-depth technical results obtained through the FAMES Pilot Line project on the development of FD-SOI at 10nm and 7nm nodes, combined with non-volatile memories (NVM) and 3D options, RF components and smart PMIC (Power Management Integrated Circuit), providing a pathway to deliver high-performance, low-power consumption solutions for future chips.

With the highlight talk: Next generations of FD-SOI technology for low-power and RF applications

by Thierry Poiroux (CEA-Leti, FR) and Valeriya Kilchytska (UCLouvain, BE)

IEEE EDS/SSCS/CAS MQ in Palma

IEEE EDS/SSCS/CAS Mini-Colloquium

FRIDAY 11 September

Sa Riera Building

C/ de Miquel dels Sants Oliver, 2

07122 Palma

IEEE EDS/SSCS/CAS MQ PROGRAM

9:00 - 09:05 Opening

9:05-9:15 Tribute to Prof. Michael S. Shur

9:05-9:15 Tribute to Prof. José Epifânio da Franca

​​​​9:15-10:05 Leveraging semiconductor technology for the benefit of society

Fernando Guarin (Director of IEEE Division I)

10:05-10:55 Power efficient WBG devices for the green transition

Mikael Ostling (KTH, SE)

10:55-11:25 Coffee Break

11:25-12:15 Holistic solutions to future computing - not only scaling

Francesca Iacopi (Purdue University, US)

12:15-13:05 Status of the Compact modeling and its Verilog-A standardization

Wladek Grabinski (MOS-AK, CH and IHP OpenPDK, DE)

13:05-14:25 Lunch​​

14:25-15:15 Graphene thin film technology for neural interfaces

José Antonio Garrido (ICN2, Barcelona, Spain)

15:15-16:05Energy-Efficient Analog IC Design: Exploring Solutions at De vice, Circuit and System Levels

Antonio López (Public University of Navarra, Spain)

[paper] Cryo mm-Wave Multifinger nMOSFETs

Adhi Cahyo Wijaya ,Jyh-Chyurn Guo  

Cryogenic mm-Wave Device Optimization and Modeling with Temperature and Layout Dependent Effects in Multifinger nMOSFETs and Si Substrate

Journal of the EDS, Vol. 14, 2026 935

Institute of Electronics, National Yang Ming Chiao Tung University, Hsinchu 300, Taiwan
Department of Electrical Engineering, National Yang Ming Chiao Tung University, Hsinchu 300, Taiwan

ABSTRACT: In this paper, cryogenic device optimization aimed at super-450GHz fT and fMAX and new equivalent circuit models with layout- and temperature-dependent effects (LDE and TDE) over 300K∼4K are presented. Open and short pad models incorporating TDE have been developed and verified by experimental data, showing extremely high Si substrate resistance (Rsi) at below 25K and the minimum Rsiat 77K followed by a turn around at above 77K. Interestingly, for active devices at on-state, carriers freezeout in the Si substrate at cryogenic temperature is suppressed, which motivates development of enhanced pad models for accurate deembedding and simulation of on-Si-chip devices and mm-wave circuits over 300K∼4K. For sub-40nm nMOSFETs with respectively optimized multi-finger (MF) layouts, the maximum fT and fMAX at 4K can reach up to 447GHz and 95 GHz.

FIG: (a) The full equivalent circuit model (b) physical representation for a full structure with intrinsic MOSFET model and enhanced pad model by adding Rsi0(g,d) and Csi0(g,d) for accurate simulation and deembedding at cryo-temp.

Acknowledgement: This work was supported in part by the National Science and Technology Council (NSTC) under Grant NSTC-114-2221-E-A49-206.