Synopsys: The 23rd MOS-AK/ESSERC Compact Modeling Workshop in Palma de Mallorca brings together the international community advancing SPICE/Verilog-A modeling, OpenPDKs, and open-source IC design flows. Since 2002 ESSEDRC/ESSCIRC in Porto, MOS-AK has been the leading forum connecting technology developers, circuit designers, and FOSS CAD/EDA contributors, supporting knowledge exchange and strengthening the open semiconductor ecosystem. This year's program showcases cutting-edge developments: GaN MOS-HEMT compact models for emerging OpenPDKs, AI/ML-driven modeling workflows replacing manual tuning, cryogenic FD-SOI model libraries, fully open-source RFIC design case studies using IIC-OSIC-TOOLS, reliability insights for advanced CMOS and RF technologies, and a new OpenPDK MOSFET matching matrix IC enabling fast mismatch characterization. The workshop organizers are inviting engineers, researchers, and students who want a clear, practical view of modern device models and open simulation frameworks. It directly supports global OpenPDK adoption and aligns with European ODE4EC-AMS activities, promoting accessible, reproducible, and future-ready IC design methodologies.
| 9:30 - 11:00 | W7 Workshop Opening |
| T_1 | ODE4EC-AMS OpenPDK: the Status and Roadmap Wladek Grabinski IHP OpenPDK (D) |
| T_2 | Advances in Open-Source Verilog-A Compilation and Simulatio> Arpad Buermen Uni. Ljubljana (SL)  |
| T_3 | Compact Modeling of GaN MOS-HEMTs for Open PDKs Ashkhen Yesayan EPFL (CH)  |
| T_4 | From Manual Tuning to Agentic AI: Transforming Device Modeling with AI/ML Roberto Tinti Keysight (US)  |
| 11:00 - 11:30 | Coffee Break |
| T_5 | Development of Cryogenic Model Libraries for FD-SOI Transistors Phanish Chava AdMOS (D)  |
| T_6 | Open-Source RFIC Design: Case Studies Using IIC-OSIC-TOOLS Georg Zachl JKU Linz (A)  |
| T_7 | Reliability topics for the miniaturization and qualification and OpenSilicon perspective Fernando Guarin IEEE EDS D1 (US)  |
| P_1 | [Poster] OpenPDK MOSFET Matching Matrix IC Juan Brito CEITEC (BR) |
| SSCS | Code-a-Chip Award Ceremony Akira Tsuchiya SSCS TC-OSE  |
| 13:00-14:00 | End of the W7 Workshop and Lunch Break |
The MOS-AK workshop was followed by ESSERC W2 Joint Workshop FAMES Pilot Line and SiNANO Institute reviwing the FDSOI Pilot Line Insights and Perspective. W2 was the first to present in-depth technical results obtained through the FAMES Pilot Line project on the development of FD-SOI at 10nm and 7nm nodes, combined with non-volatile memories (NVM) and 3D options, RF components and smart PMIC (Power Management Integrated Circuit), providing a pathway to deliver high-performance, low-power consumption solutions for future chips.
With the highlight talk: Next generations of FD-SOI technology for low-power and RF applications
by Thierry Poiroux (CEA-Leti, FR) and Valeriya Kilchytska (UCLouvain, BE)
