Showing posts with label EDA. Show all posts
Showing posts with label EDA. Show all posts

Apr 29, 2021

[PhD] VLSI Interconnect Reliability

Shaoyi Peng
Modeling and Simulation Methods for VLSI Interconnect Reliability Focusing 
on Time Dependent Dielectric Breakdown
PhD Dissertation in Electrical Engineering
University of California Riverside
https://escholarship.org/uc/item/966241xk (March 2021)

Abstract: Time dependent dielectric breakdown (TDDB) is one of the important failure mechanisms for Copper (Cu) interconnects that are used in VLSI circuits. This reliability effect becomes more severe as the space between wires is shrinking and low-k dielectric materials (low electrical and mechanical strength) are used. There are many studies and theories focusing on the physics of it. However, there is limited research from the electronics design automation (EDA) perspective on this topic, aiming to evaluate, or alleviate it from the perspective of designing a VLSI chip. This thesis compiles several studies into evaluating TDDB on the circuit level, and engineering methods that help the evaluation. The first work extends the study of a published physics model on simplified yet practical cases. It simplifies the calculation of lifetime by deriving an analytic solution and applying fitting methods. The second study proposes a new way to evaluate lifetime of a chip by extending the models of simple interconnect structures to the complete chip. This method is more robust as it focuses more on a complete chip. However, heavy dependence of finite element method (FEM) makes the flow very slow. The third study adopts machine learning methods to accelerate this slow evaluation process. The proposed method is also applicable to other similar electrostatics applications. Last but not least, the fourth study focuses on a GPU based LU factorization algorithm, which, on a broader aspect, is a universal numerical algorithm used in many different simulation applications, which can be helpful to TDDB evaluations as it can be used in FEM.
Fig: Structure of two copper interconnect wires and the IMD in the cross-section SEM image after TDDB failure [sem]
REF
[sem] N. Suzumura, S. Yamamoto, D. Kodama, K. Makabe, J. Komori, E. Murakami, S. Maegawa, and K Kubota. A new TDDB degradation model based on Cu ion drift in Cu interconnect dielectrics. In IEEE Int. Reliability Physics Symposium (IRPS), pages 26–30, 2006.

Feb 26, 2021

[DAY 2] 1st Asia/South Pacific MOS-AK Workshop

Arbeitskreis Modellierung von Systemen und Parameterextraktion
Modeling of Systems and Parameter Extraction Working Group
1st Asia/South Pacific MOS-AK Workshop
(virtual/online) FEB. 25-26, 2021

Day2: FEB.26
Session C Chair: Sadayuki Yoshitomi, Kioxia (J)

[8] eSim: An open source CAD software for circuit simulation
Kannan Moudgalya
IIT Bombay (IN)

[9] A modular approach to next generation Qucs
Felix Salfelder and Mike Brinson
QUCS Team; Centre for Communications Technology, London Metropolitan University (UK)

[12] Machine learning-based approach to model and analyze GaN power devices
Tian-Li Wu
National Yang Ming Chiao Tung University, Taiwan (TW)

[11] TCAD-inspired compact modeling approach
Sung-Min Hong and Kwang-Woon Lee
Gwangju GIST (KR)

Session D Chair: Sheikh Aamir Ahsan, NIT Srinagar (IN)
[10] An Innovative Technique for Ultrafast Carrier Dynamics and THz Conductivities of Semiconductor Nanomaterials
Praveen Kr. Saxena and Fanish Kr. Gupta
Tech Next Lab, Lucknow (IN)

[13] Compact Modeling of 3D NAND Flash Memory for Diverse Unconventional Analog Applications
Shubham Sahay
IIT Kanpur (IN)

[14] Steep Subthreshold Slope PN-Body Tied SOI-FET for Ultralow Power LSI, Sensor, and Neuromorphic Chip
Takayuki Mori and Jiro Ida
Kanazawa Institute of Technology, Nonoichi (J)

[Pic] Group photo of selected MOS-AK participants attending 2nd Day of the workshop


[DAY 1] 1st Asia/South Pacific MOS-AK Workshop

Arbeitskreis Modellierung von Systemen und Parameterextraktion
Modeling of Systems and Parameter Extraction Working Group
1st Asia/South Pacific MOS-AK Workshop
(virtual/online) FEB. 25-26, 2021

DAY 1: FEB. 25, 2021
Session A Chair: Usha Gogineni, ams AG, Hyderabad (IN)

[1] New Insights in Low Frequency Noise Characteristics in PE-BJTs
Peijian Zhang and Ma Long
Science and Technology on Analog Integrated Circuit Laboratory; WHU (CN), Keysight Technologies (US)

[2] Direct white noise characterization of short-channel MOSFETs
K. Ohmori and S. Amakawa
DeviceLab, Tsukuba (J)

[3] SPICE Modeling of 2D-material based FETs with Schottky-barrier contacts
Sheikh Aamir Ahsan
Nanoelectronics Research and Development Group, NIT Srinagar, Jammu and Kashmir (IN)


[4] Physics-based model of SiC MOSFETs including high voltage and current regions
Sourabh Khandelwal, Cristino Salcines, and Ingmar Kallfass
Macquarie University Sydney (AU), University of Stuttgart (D)

Session B Chair: Daniel Tomaszewski, IMiF, Warszaw (PL)
[5] Compact Modeling for Gate-All-Around FET Technology
Avirup Dasgupta
IIT Roorkee (IN)


[6] BSIM-HV: Advanced High Voltage MOSFET Compact Model
Harshit Agarwal
IIT Jodhpur (IN)

[7] ASCENT+ Transnational Access for the nanoelectronics
Georgios Fagas
Tyndall (IE)

[Pic] Group photo of selected MOS-AK participants attending 1st Day of the workshop

Jun 2, 2020

Webinars by IEEE Photonics Society Student Chapter

The IEEE Photonics Society Student Chapter of Mangalam College of Engineering has organized a series of the webinars to take away some useful stuffs during current COVID-19 quarantine. The webinar #5 was on:
FOSS TCAD/EDA Tools for Semiconductor Device Modeling
Dr. Wladyslaw Grabinski  
MOS-AK Association   



Jul 12, 2019

IEEE ICECS 2019 paper submission deadline

ICECS 2019 paper deadline submission is approaching fast: July 15th, 2019

Please distribute this reminder to possible contributors and interested researchers and colleagues. Topics of interest include but are not limited to:

• Analog/mixed-signal/RF circuits
• Biomedical and Bio-Inspired Circuits and Systems
• EDA, Test and Reliability
• Digital circuits and systems
• Linear and Non-linear Circuits
• Low-Power Low-Voltage Design
• Microsystems
• Neural networks, Machine and Deep Learning
• Sensors and Sensing Systems
• Signal Processing, Image and Video
• VLSI Systems and Applications

The technical committee invites authors to submit 4-page papers in standard IEEE double-column format, including references, figures and tables, to clearly present the work, methods, originality, significance and applications of the techniques discussed.

Maurizio Valle; IEEE ICECS 2019 General Chair
https://www.ieee-icecs2019.org/

Oct 15, 2018

FOSDEM 2019 CAD and Open Hardware Devroom Call for Participation

This is the call for participation in the FOSDEM 2019 devroom on Computer Aided Design (CAD) tools and Open Hardware, to be held on Sunday 3 February 2019 in Brussels, Belgium. We are looking for contributions under the form of talks and tutorials covering the following main topics:
  • Printed Circuit Board (PCB) design tools (e.g. KiCad and gEDA)
  • Analogue and digital simulators (e.g. ngspice, Qucs, Gnucap, Xyce, GHDL, Icarus and Verilator)
  • Any other EDA tools such as high-level tools for digital hardware design (e.g. Migen) and HDL synthesis tools (e.g. Yosys)
  • Field solvers such as openEMS
  • Mechanical 2D and 3D CAD tools such as LibreCAD, FreeCAD, OpenSCAD and SolveSpace
  • Open Hardware projects such as the Teres laptop and the lowRISC SoC
  • Inter-project opportunities for collaboration
We hope to provide an opportunity for attendees to bring themselves up to date on the latest FOSS CAD and Open Hardware developments, share knowledge and identify opportunities to collaborate on development tasks. This devroom is an evolution of the EDA devroom we organised in 2015, 2016 and 2017, which enlarged its scope in the CAD and Open
Hardware devroom in 2018.

Please submit your proposals at
https://penta.fosdem.org/submission/FOSDEM19 
before 1 December 2018.

Important dates
8 December 2018: deadline for submission of proposals
15 December 2018: announcement of final schedule
3 February 2019: devroom day

Oct 30, 2017

FOSDEM 2018 CAD and Open Hardware Devroom Call for Participation


This is the call for participation in the FOSDEM 2018 devroom on Computer Aided Design (CAD) tools and Open Hardware, to be held on Saturday 3 February 2018 in Brussels, Belgium. We are looking for contributions under the form of talks and tutorials covering the following main topics:
  • Printed Circuit Board (PCB) design tools (e.g. KiCad and gEDA)
  • Analogue and digital simulators (e.g. ngspice, Qucs, Gnucap, Xyce,GHDL, Icarus and Verilator)
  • Any other EDA tools such as high-level tools for digital hardware design (e.g. Migen) and HDL synthesis tools (e.g. Yosys)
  • Field solvers such as openEMS
  • Mechanical 2D and 3D CAD tools such as LibreCAD, FreeCAD, OpenSCAD andSolveSpace
  • Open Hardware projects such as the Teres laptop and the lowRISC SoC
  • Inter-project opportunities for collaboration
We hope to provide an opportunity for attendees to bring themselves up to date on the latest FOSS CAD and Open Hardware developments, share knowledge and identify opportunities to collaborate on development tasks. This devroom is an evolution of the EDA devroom we organised in 2015, 2016 and 2017.

The submission process: Please submit your proposals at

If you already have a Pentabarf account (for example as a result of having submitted a proposal in the past), make sure you use it to log in and submit your proposal. Do not create a new account if you already have one. Please provide a bit of information about yourself under Person -> Description -> Abstract. When you submit your proposal (creating an "Event" in Pentabarf), make sure you choose the "CAD and Open Hardware Devroom" in the track drop-down menu. Otherwise your proposal might go unnoticed. Fill in at least a title and abstract for the proposed talk and a suggested duration. Bear in mind that a lot of the value in these meetings comes from the discussions, so please be reasonable regarding the duration of the talk.

Important dates
  • 1 December 2017: deadline for submission of proposals
  • 8 December 2017: announcement of final schedule
  • 3 February 2018: devroom day
Recordings: The FOSDEM organisers hope to be able to live-stream and record all the talks. The recordings will be published under the same licence as all FOSDEM content (CC-BY). Only presentations will be recorded, not informal discussions and whatever happens during the lunch break. By agreeing to present at FOSDEM, you automatically give permission to be recorded. The organisers will agree to make exceptions but only for exceptional and well-reasoned cases.

Mailing list: Feel free to subscribe to the mailing list of the CAD and Open Hardware devroom to submit ideas, ask questions and generally discuss about the event:

Spread the word!

Dec 28, 2016

FOSS CAD research is in the spotlight

The conference paper "FOSS as an efficient tool for extraction of MOSFET compact model parameters" reached 20 reads at the researchgate.net

FOSS as an efficient tool for extraction of MOSFET compact model parameters
D. Tomaszewski, G. Głuszko, M. Brinson, V. Kuznetsov and W. Grabinski
MIXDES 2016, Lodz, pp. 68-73.


Abstract—A GNU Octave – based application for device-level compact model evaluation and parameter extraction has been developed. The applications main features are as follows: experimental I-V data importing, generating input data for different circuit simulation programs, running the simulation program to calculate I-V characteristics of the specified models, calculating model misfit and its sensitivity to selected parameter variation, and the comparison of experimental and simulated characteristics. Measured I-V data stored by different measurement systems are accepted. Circuit simulations may be done with Ngspice, Qucs and LTSpiceIV. Selected aspects of the application are presented and discussed. 

Oct 20, 2016

Free Semiconductor Books on SemiWiki

Download free PDF versions of three pivotal semiconductor books available on SemiWiki.com:
  1. Mobile Unleashed: The History of ARM
  2. Fabless: The Transformation of the Semiconductor Industry
  3. EDAGraffiti: 25 years of experience in EDA
Only registered SemiWiki members can access these wiki pages so if you are not already a member please join as a guest: https://www.semiwiki.com/forum/register.php

Oct 14, 2016

FOSDEM 2017 EDA Devroom Call for Participation



This is the call for participation in the FOSDEM 2017 devroom on Free/Open Source Software (FOSS) Electronic Design Automation (EDA) tools, to be held on Sunday 5 February 2017 in Brussels, Belgium. We are looking for contributions under the form of talks and tutorials covering the following main topics:
  • Printed Circuit Board (PCB) design tools (e.g. KiCad and gEDA)
  • Analogue and digital simulators (e.g. ngspice, Qucs, Gnucap, Xyce, GHDL, Icarus and Verilator)
  • Any other EDA tools such as high-level tools for digital hardware design (e.g. Migen) and HDL synthesis tools (e.g.Yosys)
  • Inter-project opportunities for collaboration
We hope to provide an opportunity for attendees to bring themselves up to date on the latest FOSS EDA developments, share knowledge and identify opportunities to collaborate on development tasks. Have a look at last year's event for a taste of what the EDA devroom is about.

The submission process
Please submit your proposals at 
before 1 December 2016.

If you already have a Pentabarf account (for example as a result of having submitted a proposal in the past), make sure you use it to log in and submit your proposal. Do not create a new account if you already have one. Please provide a bit of information about yourself under Person -> Description -> Abstract. When you submit your proposal (creating an "Event" in Pentabarf), make sure you choose the "Electronic Design Automation (EDA) devroom" in the track drop-down menu. Otherwise your proposal might go unnoticed. Fill in at least a title and abstract for the proposed talk and a suggested duration. Bear in mind that a lot of the value in these meetings comes from the discussions, so please be reasonable regarding the duration of the talk.

Important dates
  • 1 December 2016: deadline for submission of proposals
  • 11 December 2016: announcement of final schedule
  • 5 February 2017: devroom day
Recordings
The FOSDEM organisers hope to be able to live-stream and record all the talks. The recordings will be published under the same licence as all FOSDEM content (CC-BY). Only presentations will be recorded, not informal discussions and whatever happens during the lunch break. By agreeing to present at FOSDEM, you automatically give permission to be recorded. The organisers will agree to make exceptions but only for exceptional and well-reasoned cases.
Mailing list

Feel free to subscribe to the mailing list of the EDA devroom to submit ideas, ask questions and generally discuss about the event.

Spread the word!
This is the third EDA devroom at FOSDEM. The first two were very well received. Let's make sure as many projects and developers as possible are present. Thanks!

Feb 5, 2016

Free Computational Electromagnetic Modeling Codes

The software in this list is either free or available at a nominal charge and can be downloaded over the internet. Some of the codes require the user to register with the distributor's web site. If you are familiar with other free EM modeling software that that should be added to this list, please send the name of the software, a hypertext link, and a brief description to CVEL-L@clemson.edu.

This page has been translated into Italian here, Serbo-Croatian here, Slovakian here, Swedish here and Polish here and here.

(Page last update: December 14, 2015 )

Jan 19, 2016

FOSDEM 2016 EDA Devroom

FOSDEM 2016: EDA Devroom
Room: AW1.121 
Saturday, 30 January 2016

Software developers have a much easier time sharing their developments than hardware designers. When you put a piece of code on the Web, you don't ask yourself if others will have the freedom and resources to access a text editor to look at it and modify it, or a compiler or interpreter to have the code do something useful. The landscape for hardware designs is more complicated. The dominant design and simulation tools are proprietary, and there is not even a de-facto proprietary standard format to share designs. The Electronic Design Automation (EDA) Devroom looks at recent progress in Free CAD/EDA Tools for hardware design and simulation, and serves as a meeting place for discussion about future collaborations and FOSS developments. Come and see how some of these tools are actually catching up, and sometimes even more, in terms of features and quality.

[EDA Devroom Detailed Agenda]

Oct 29, 2015

[Call for Participation] FOSDEM 2016 Electronic Design Automation Devroom

 Call for Participation 
FOSDEM 2016 Electronic Design Automation Devroom 

This is the call for participation in the FOSDEM 2016 devroom on Free/Open Source Software (FOSS) Electronic Design Automation (EDA) tools, to be held on Saturday 30 January 2016 in Brussels, Belgium. We are looking for contributions under the form of talks covering the following main topics:
  • Printed Circuit Board (PCB) design tools (e.g. KiCad and gEDA)
  • Analogue and digital simulators (e.g. ngspice, Qucs, Gnucap, Xyce, GHDL, Icarus and Verilator)
  • Any other EDA tools such as high-level tools for digital hardware design (e.g. Migen)
  • Inter-project opportunities for collaboration
We hope to provide an opportunity for attendees to bring themselves up to date on the latest FOSS EDA developments, share knowledge and identify opportunities to collaborate on development tasks. Have a look at last year's event for a taste of what the EDA devroom is about.
The submission process
Please submit your proposals at https://penta.fosdem.org/submission/FOSDEM16 
before 4 December 2015.

If you already have a Pentabarf account (for example as a result of having submitted a proposal in the past), make sure you use it to log in and submit your proposal. Do not create a new account if you already have one. Please provide a bit of information about yourself under Person -> Description -> Abstract. When you submit your proposal (creating an "Event" in Pentabarf), make sure you choose the "EDA devroom" in the track drop-down menu. Otherwise your proposal might go unnoticed. Fill in at least a title and abstract for the proposed talk and a suggested duration. Bear in mind that a lot of the value in these meetings comes from the discussions, so please be reasonable regarding the duration of the talk.
Important dates
  • 4 December 2015: deadline for submission of proposals
  • 18 December 2015: announcement of final schedule
  • 30 January 2016: devroom day

Jan 9, 2013

10th IWCM Workshop Program

10th International Workshop on Compact Modeling 

January 22 (Tue), 2013 

Pacifico Yokohama, Room 419

Yokohama, Japan

Time
#
Title
Authors
Affiliation
9:00-9:10

Opening: H. J.  Mattausch (Workshop Chair)




Power Devices   Chair: D. Navarro


9:10-9:30
1
HiSIM_HV Temperature Modeling for Multi-Geometry LDMOS: Comparison of the Temperature Flag Options
Y. Iino
Silvaco Japan
9:30-9:50
2
Analysis and Further Improvements of the Drain-Resistance Modeling in HiSIM_HV
T. Umeda et al.
Hiroshima University
9:50-10:10
3
Floating-Base Effect Modeling for IGBT Structure using Potential Modification
T. Yamamoto
et al.
Denso
10:10-10:30

- Break -




Novel FET Structures Chair: T. Nakagawa


10:30-10:50
4
Study on Dynamic Threshold Nanowire Tunnel FET
A. Zhang et al.
Peking University
Shenzhen
10:50-11:10
5
A DC Model of TFETs for SPICE Simulations
L. Zhang and M. Chan
HK UST 
11:10-11:30
6
A Surface Potential Based Compact Model of Organic Thin-Film Transistor for Circuit Simulation
T.K. Maiti et al.
Hiroshima University
11:30-11:40

-  Break -




Optical and Wireless Chair: J. He


11:40-12:00
7
An Embedded Modulation of Silicon Germanium FIN-LED - A simulation study
J. Kwon et al.
Seoul National
University
12:00-12:20
8
Predicting Key Parameters of Inductive Power Links
S. Raju et al.
HK UST 
12:20-14:00

- Lunch Break -




Aging and Degradation Chair: M. Miura-Mattausch


14:00-14:40
9
Invited Keynote: Interaction of Bloch Carrier and Bound State in the Reliability Modeling
Y.J. Park and
S. Choi
Seoul National
University
14:40-15:00
10
Development of Unified Predictive NBTI Model and its Application for Circuit Aging Simulation
C. Ma et al.
Hiroshima University, STARC
15:00-15:20
11
Effects of Nonlocal Concentration of Carriers in the Oxide for NBTI Simulation
S. Rhee et al.
Seoul National
University
15:20-15:40

-  Break -




Fabrication Variation Chair: Y. J. Park


15:40-16:00
12
Parameter Extraction for Statistical Variation of HV-MOSFETs
Y. Ueda et al.
Ricoh, STARC
16:00-16:20
13
Analysis of Gate-Length Dependence of MOSFET Random Variation by Using HiSIM-RP
S. Kumashiro
et al.
Renesas Electronics
16:20-16:40
14
Random Dopant Fluctuation Effects on Double Gate Tunneling FET Performance
Y. Zhu et al.
Peking University
Shenzhen
16:40-16:50

Closing: H.J. Mattausch (Workshop Chair)



Oct 5, 2012

QucsStudio 1.4.2

A new version of QucsStudio has just been released for general use. The latest version is mainly  bug fixes but does contain a number of new/improved features. A list of the changes are given below:

  • some corrections in help system
  • component names in noise contribution analysis with subcircuit prefix
  • reduced time step warnings in transient analysis
  • bugfix: differential voltages in equations
  • in equations: allow suffix in node names
  • bugfix: directory MinGW\mingw32\bin\ exists again
  • bugfix: crash in diagram dialog if clicking on empty variable area
  • new component: photodiode
  • new equation function: stoa()
  • bugfix: spaces allowed between function name and "("
  • added InP permittivity in property list
  • bugfix: correct text in C++ symbol string
  • error message for wrong index in equation variables

This is likely to be one of the last releases in the QucsStudio 1.4 series.  Work has started on QucsStudio series 2.0.0.  QucsStudio 2.0.0 is expected to offer users significant improvements in simulation and modelling capabilities.  The first of the new releases will coincide with the tenth anniversary of the first release of Qucs next year.

QucsStudio can be downloaded from the QucsStudio homepage at http://www.mydarc.de/DD6UM/QucsStudio/qucsstudio.html

Contact: Mike Brinson

Jul 17, 2009

20th Anniversary of Innovation

View from The Top Executive Interviews "20th Anniversary of Innovation", John Tanner, CEO Tanner EDA Follow audio interview...