[chapter] Extraction for a 65nm FG Transistor.

[chapter] Cong, T.D., Hoang, T. (2023). A Methodology of Extraction DC Model for a 65 nm Floating-Gate Transistor. 

In: Dao, NN., Thinh, T.N., Nguyen, N.T. (eds) Intelligence of Things: Technologies and Applications. ICIT 2023. Lecture Notes on Data Engineering and Communications Technologies, vol 187. Springer, Cham. https://doi.org/10.1007/978-3-031-46573-4_19

Abstract: Floating-gate Metal-Oxide Semiconductor (MOS) has been investigated and applied in many applications such as artificial intelligence, analog mixed-signal, neural networks, and memory fields. This study aims to propose a methodology for extracting a DC model for a 65 nm floating-gate MOS transistor. The method in this work uses the combination architecture of MOS transistor, capacitance, and voltage-controlled voltage source which can archive a high accuracy result. Moreover, the advantage of the method is that the MOS transistor was a completed model which enhances the flexibility and accuracy between a fabricated device and modeled architecture. In our work, the industrial standard model Berkeley Short-channel IGFET Model (BSIM) 3v3.1, level 49 was deployed, and the DC simulation was obtained with the use of LTspice tool.

[paper] CMOS floating-gate device for quantum control hardware

Michele Castriotta¹, Enrico Prati², Giorgio Ferrari¹

Cryogenic characterization and modeling of a CMOS floating-gate device 

for quantum control hardware

preprint arXiv:2110.02315, 2021

1 Dipartimento di Elettronica, Informazione e Bioingegneria, Politecnico di Milano (I)
2 Istituto di Fotonica e Nanotecnologie, Consiglio Nazionale delle Ricerche (I)

Abstract - We perform the characterization and modeling of a floating gate device realized with a commercial 350-nm CMOS technology at cryogenic temperature. The programmability of the device offers a solution in the realization of a precise and flexible cryogenic system for qubits control in large-scale quantum computers. The device stores onto a floating-gate node a non-volatile charge, which can be bidirectionally modified by Fowler-Nordheim tunneling and impact-ionized hot electron injection. These two injection mechanisms are characterized and modeled in compact equations both at 300 K and 15 K. At cryogenic temperature, we show a fine-tuning of the stored charge compatible with the operation of a precise analog memory. Moreover, we developed accurate simulation models of the proposed floating-gate device that set the stage for designing a programmable analog circuit with better performances and accuracy at a few Kelvin. This work offers a solution in the design of configurable analog electronics to be employed for accurately read out the qubit state at deep-cryogenic temperature.

Fig: Simplified layout of the p-type floating-gate device under test. The capacitive coupling to the floating-gate node  is realized with the poly 2 control gate.

Acknowledgments: This work was supported by QUASIX Grant from  Italian Space Agency. This work was partially performed at Polifab, the  micro- and nanofabrication facility of Politecnico di Milano