[paper] Bionic Neural Probe

Yu Zhou, Huiran Yang, Xueying Wang, Heng Yang, Ke Sun, Zhitao Zhou, Liuyang Sun, Jianlong Zhao, Tiger H. Tao and Xiaoling Wei

A mosquito mouthpart-like bionic neural probe

Microsystems & Nanoengineering volume 9, Article number: 88 (2023)

DOI: 10.1038/s41378-023-00565-5

Abstract: Organic electronics can be biocompatible and conformable, enhancing the ability to interface with tissue. However, the limitations of speed and integration have, thus far, necessitated reliance on silicon-based technologies for advanced processing, data transmission and device powering. Here we create a stand-alone, conformable, fully organic bioelectronic device capable of realizing these functions. This device, vertical internal ion-gated organic electrochemical transistor (vIGT), is based on a transistor architecture that incorporates a vertical channel and a miniaturized hydration access conduit to enable megahertz-signal-range operation within densely packed integrated arrays in the absence of crosstalk. These transistors demonstrated long-term stability in physiologic media, and were used to generate high-performance integrated circuits. We leveraged the high-speed and low-voltage operation of vertical internal ion-gated organic electrochemical transistors to develop alternating-current-powered conformable circuitry to acquire and wirelessly communicate signals. The resultant stand-alone device was implanted in freely moving rodents to acquire, process and transmit neurophysiologic brain signals. Such fully organic devices have the potential to expand the utility and accessibility of bioelectronics to a wide range of clinical and societal applications.

FIG: Multifunctional biomimetic neural probe system, with multichannel flexible electrode array and high sensitivity sensor array. 

[paper] Vertical Junction-Less Nanowire FETs

C. Maneux (University of Bordeaux), C. Mukherjee (CNRS), M. Deng (University of Bordeaux), G. Larrieu (CNRS), Y. WANG, B. Wesling, and H. Rezgui (University of Bordeaux)

Strategies for Characterization and Parameter Extraction of Vertical Junction-Less Nanowire FETs Dedicated to Design Technology Co-Optimization

H02-1863 (Invited) at 243rd ECS Meeting and SOFC-XVIII 

Boston, MA, May 29 - June 2, 2023

Abstract: In the era of emerging computing paradigms and artificial neural networks, hardware and functionality requirements are in the surge. In order to meet low power and latency criteria, new architectures for in-memory computing are being explored as alternatives to traditional von Neumann machines, which requires technological breakthrough at the semiconductor device level such as vertical gate-all-around junctionless nanowire field effect transistors (VNWFET), that can address many process challenges such as downscaling, short-channel effects, compactness and electrostatic control. Its integration in the mainstream design flow is not straightforward and requires design technology co-optimization (DTCO) at an early stage. This invited paper explores strategies for accurate characterization and parameter extraction of the VNWFETs to feed the DTCO compact models

Fig: Final verification using full 3D multiphysics device thermal simulation, accounting for both ballistic and diffusive heat flux

[paper] Vertical III-V Nanowire MOSFETs on Si

Olli-Pekka Kilpi, Markus Hellenbrand, Johannes Svensson, Axel R. Persson, Reine Wallenberg, Erik Lind, Member, IEEE, and Lars-Erik Wernersson

High-Performance Vertical III-V Nanowire MOSFETs on Si With gm > 3 mS/μm

in IEEE EDL vol. 41, no. 8, pp. 1161-1164, Aug. 2020

DOI: 10.1109/LED.2020.3004716

Abstract: Vertical III-V nanowire MOSFETs have demonstrated excellent performance including high transconductance and high Ion. One main bottleneck for the vertical MOSFETs is the large access resistance arising from the contacts and ungated regions. We demonstrate a process to reduce the access resistance by combining a gate-last process with ALD gate-metal deposition. The devices demonstrate fully scalable gm down to Lg = 25 nm. These vertical core/shell InAs/InGaAs MOSFETs demonstrate gm = 3.1 mS/μm and Ron = 190 μm. This is the highest gm demonstrated on Si. Transmission line measurement verifies a low contact resistance with RC = 115 μm, demonstrating that most of the MOSFET access resistance is located in the contact regions.

FIG: (a) of the MOSFET structure demonstrating benefit of the TiN gate metal;

(b )output characteristics of the vertical nanowire MOSFET 

with 90 nanowires, LG = 25 nm and diameter 17 nm.

Acknowledgment: This work was supported in part by the Swedish Research Council, in part by the Knut and Alice Wallenberg Foundation, in part by the Swedish Foundation for Strategic Research, and in part by the European Union H2020 Program INSIGHT under Grant 688784.