[paper] Statistical model of the NBTI-induced ΔVth, ΔSS, and Δgm degradations in advanced pFinFETs

Statistical model of the NBTI induced threshold voltage, subthreshold swing, and transconductance degradations in advanced pFinFETs
J. Franco, B. Kaczer, S. Mukhopadhyay, P. Duhan, P. Weckx, Ph.J. Roussel, T. Chiarella, L.-Å. Ragnarsson, L. Trojman, N. Horiguchi, A. Spessot, D. Linten, A. Mocuta
2016 IEEE International Electron Devices Meeting (IEDM), San Francisco, CA, USA, 2016, pp. 15.3.1-15.3.4.
DOI: 10.1109/IEDM.2016.7838422

Abstract

We study the stochastic NBTI degradation of pFinFETs, in terms of ΔVth, ΔSS, and Δgm. We extend our Defect-Centric model to describe also the SS distribution in a population of devices of any area, at any stage of product aging. A large fraction of nanoscale devices is found to show a peak g m improvement after stress. We explain this effect in terms of the interaction of individual defects with the percolative channel conduction, and we propose a statistical description of g m aging. Our Vth, SS, and gm aging models are pluggable into reliability-enabled compact models to estimate design margins for a wide variety of circuits. Selected nanoscale device characteristics resulting from 3 percolation paths, generated with the EKV model [read more...]

[paper] Processes of AM-PM Distortion in Large-Signal Single-FET Amplifiers

Processes of AM-PM Distortion in Large-Signal Single-FET Amplifiers

S. Golara, S. Moloudi and A. A. Abidi, " 

in IEEE Transactions on Circuits and Systems I: Regular Papers, 

vol. 64, no. 2, pp. 245-260, Feb. 2017; doi: 10.1109/TCSI.2016.2604000

Abstract: Using an appropriate formulation of field-effect transistor (FET) current as a nonlinear function of terminal voltages, and a simplified model of gain compression in common source amplifiers, we are able to identify four principal sources of amplitude-to-phase (AM-PM) distortion. A new analysis shows the varactor effect of gate-source capacitance on AM-PM distortion, and the changing Miller-multiplied gate-drain capacitance as the field-effect transistor (FET) is driven into compression. The phase shift in the load impedance at the frequency of operation and incomplete suppression of 2nd harmonic by a resonant load of limited Q are explained and analyzed. We are able to identify the dominant mechanism of AM-PM distortion in various practical circuits, which then suggests methods of remediation. The analysis was put to test by predicting the measured AM-PM distortion of power amplifiers reported in the literature. Good agreement is found in all cases, with insights gained into the dominant cause of distortion in each case. In this paper, AM-PM distortion is first defined in Section II. In Section III, the EKV model of the MOSFET is briefly presented and dominant mechanisms are explained. In Section IV the analysis is compared against measured data to validate the theory and Section V summarizes the conclusions [read more...]

[chapter] Near-Threshold Digital Circuits for Nearly-Minimum Energy Processing

Near-Threshold Digital Circuits for Nearly-Minimum Energy Processing

Massimo Alioto

Department of Electrical & Computer Engineering, National University of Singapore

in Enabling the Internet of Things; pp 95-148 

DOI: 10.1007/978-3-319-51482-6_4

This chapter addresses the challenges and the opportunities to perform computation with nearly-minimum energy consumption through the adoption of logic circuits operating at near-threshold voltages. Simple models are provided to gain an insight into the fundamental design tradeoffs. A wide set of design techniques is presented to preserve the nearly-minimum energy feature in spite of the fundamental challenges in terms of performance, leakage and variations. Emphasis is given on debunking the incorrect assumptions that stem from traditional low-power common wisdom at above-threshold voltages. The traditional EKV model is very useful for quick estimates, but it oversimplifies the IV characteristics that is observed in actual nanometer CMOS technologies [read more...]

[paper] Electronically tunable MOSFET-based resistor

Electronically tunable MOSFET-based resistor used in a variable gain amplifier or filter

W. L. Tan, C. H. Chang and L. Siek

Nanyang Technological University; Singapore 

2016 International Symposium on Integrated Circuits (ISIC), Singapore, 2016, pp. 1-4.

doi: 10.1109/ISICIR.2016.7829715

Abstract: We present a new design of an electronically tunable linear MOS resistor circuit that operates in the subthreshold saturation region, supported with mathematical derivations and simulation results using CSM0.13µm technology. For a given potential difference across the MOS resistor, its gate voltage will be automatically biased through feedback to provide the correct amount of current based on the desired resistance set through the bias current. Equating the output current of the OTA with the subthreshold equation of the EKV model. In comparison with an existing design, the proposed design offers equal tunabilty with 36 less transistors for unidirectional current and 28 less transistors with one more bias current transistor for bidirectional current. A bias current ranging between 10nA to 100nA offers a tunable linear resistance between 20MΩ to 140MΩ [read more...]

[paper] Modeling, simulation and implementation of circuit elements in an open-source tool set on the FPAA

Modeling, simulation and implementation of circuit elements in an open-source tool set on the FPAA

Aishwarya Natarajan and Jennifer Hasler

Georgia Institute of Technology Atlanta USA

Analog Integr Circ Sig Process (2017), pp 1–12

doi:10.1007/s10470-016-0914-y

ABSTRACT: An open-source simulator to design and implement circuits and systems, replicating the results from the Field Programmable Analog Array (FPAA) is presented here. The fundamental components like the transistors, amplifiers and floating gate devices have been modeled based on the EKV model with minimal parameters. Systems including continuous-time filters and the analog front-end of a speech processing system have been built from these basic components and the simulation results and the data from the FPAA are shown. The simulated results are in close agreement to the experimental measurements obtained from the same circuits compiled on the FPAA fabricated in a 350 nm process [read more...]

[paper] Analysis of aging effects - From transistor to system level

Analysis of aging effects - From transistor to system level

Maike Taddiken*, Nico Hellwege, Nils Heidmann, Dagmar Peters-Drolshagen, Steffen Paul

Institute of Electrodynamics and Microelectronics,
University of Bremen, Otto-Hahn-Allee 1, Bremen 28359,Germany

ABSTRACT: Due to shrinking feature sizes in integrated circuits, additional reliability effects have to be considered which influence the functionality of the system. These effects can either result from the manufacturing process or external influences during the lifetime such as radiation and temperature. Additionally, modern technology nodes are affected by time-dependent degradation i.e. aging. Due to the age-dependent degradation of a circuit, processes on the atomic scale of the semiconductor material lead to charges in the oxide silicon interface of CMOS devices, altering the performance parameters of the device and subsequently the behavior of the circuit. With the continuous downscaling of modern semiconductor technologies, the impact of these atomic scale processes affecting the overall system characteristics becomes more and more critical. Therefore, aging effects need to be assessed during the design phase and actions have to be taken guaranteeing the correct system functionality throughout a system’s lifetime. This work presents methods to investigate the influence of age-dependent degradation as well as process variability on different levels. An operating-point dependent sizing methodology based on the gm/ID method extended to incorporate aging, which aims at developing aging-resistent circuits is presented. The basic idea of the gm/ID sizing method is the dependence of the operating point of a MOS transistor on the state of inversion in the channel, its strong relation to circuit performance and the possibility to calculate transistor dimensions.The inversion coefficient IC is a fundamental metric within the gm/ID method and numerically represents the inversion level of a MOS device formally described in the EKV MOS model. Additionally, the sensitivity of circuit performances in regard to aging can be determined. In order to investigate the reliability of a complex system on behavioral level, a modeling method to represent the performance of system components in dependence of aging and process variability is introduced. [read more...]

[paper] Field programmable analog array: A boon for analog world

Field programmable analog array: A boon for analog world

Dipti and B. V. R. Reddy,

2016 3rd International Conference on Computing for Sustainable Global Development 

(INDIACom), New Delhi, India, 2016, pp. 2975-2980.

Abstract: n analog chips designing, fabricating, and testing takes a lot of time, money and perfection. In contrast design of digital integrated circuits is fully automated now a day. Due to simpler nature of digital circuits, as compared to Analog circuits, leads to development of libraries and synthesis tools for fast synthesis of digital circuits. To reduce the cost and time-to-market CPLDs and FPGAs are generally used for prototyping of digital integrated circuits. But FPAAs i.e Field Programmable Analog Arrays are boon for designing of analog and mixed-signal Integrated Circuits because of rapid prototyping. FPAA is not only optimal for all solution in contrast to FPGAs but it also reduces the verification and designing cost. This again results from complex nature of analog circuits which needs factors like signal to noise ratio, bandwidth, frequency response, linearity etc. to be addressed. FPAAs are made using configurable analog blocks (CAB) and networks, which are used to provide required interconnection among Cabs. Like FPGAs, circuit functionality is much more sensitive to parasitics introduced by the programming devices in FPAA. So the design of FPAAs architecture and CABs are mutually dependent. To design an efficient FPAA, a designer needs to compromise between flexibility and the number of programmable switches in designing FPAA architectures and the CAB topologies. Various papers are studied for different topologies used in FPAAs and various applications designed with the use of FPAA. In March 2013, Paul Hasler come up with automated approach based on EKV model for characterization of device mismatch, second order defects with temperature. After verification of characterization current sources were created with 2.2% RMS error over dynamic range of 25dB. Field programmable gate array represents a new direction to analog and mixed signal domain keeping the idea of FPGAs in digital domain. RASP is useful for analog designers because they can save the analog components in the form of CABs. RASPER tool was developed for placement and routing of RASP 2.7 and RASP 2.8 versions Whereas GRASPER was developed for RASP 2.9.In digital circuits parasitic only affect the speed of operation but in analog circuits they plays a crucial role for circuit performance and functionality. Floating gate technology was used to simplify designing and implementation, increased system reliability, high precision, innovative approach. In near future FPAA technology will come up with better architecture, low power and more applications with less time to market.

keywords: Decision support systems, Handheld computers, Configurable analog block (CAB), Field programmable analog array (FPAA), Generic reconfigurable array specification and programming environment tool (GRASPER), Operational Transconductance Amplifier, Reconfigurable analog signal processor (RASP)

[read more...]

[ESSDERC Paper] Compact model for variability of low frequency noise due to number fluctuation effect

Compact model for variability of low frequency noise due to number fluctuation effect

N. Mavredakis and M. Bucher

2016 46th European Solid-State Device Research Conference (ESSDERC)

Lausanne, Switzerland, 2016, pp. 464-467

doi:10.1109/ESSDERC.2016.7599686

Abstract: Variability of low frequency noise (LFN) in MOSFETs is both geometry- and bias-dependent. RTS noise prevails in smaller devices where noise deviation is mostly area-dominated. As device dimensions increase, operating conditions determine noise variability maximizing it in weak inversion and increasing it with drain voltage. This dependence is shown to be directly related with fundamental carrier number fluctuation effect. A new bias- and area-dependent, physics-based, compact model for 1/f noise variability is proposed. The model exploits the log-normal behavior of LFN. The model is shown to give consistent results for average noise, variance, and standard deviation, covering bias-dependence and scaling over a large range of geometry.

Keywords: compact models, Low-frequency noise, MOSFET, Reactive power, Semiconductor device modeling, Shape, Standards, MOSFET, low frequency noise, noise variability

URL: http://ieeexplore.ieee.org/stamp/stamp.jsp?tp=&arnumber=7599686&isnumber=7598672

100 reads: Compact Device Modeling using Verilog-AMS and ADMS

Article reached 100 reads: Compact device modeling using Verilog-AMS and ADMS
Lemaitre L · Grabiński W · McAndrew C
Abstract: This paper shows how high level language as Verily-AMS can serve as support for compact modeling development of new devices. First section gives a full Verily-AMS code of a simplified bipolar transistor. Each part of the code is carefully examined and explained. Second section compared different implementations if the simplified bipolar transistor in different spice simulators. ADMS, an open-source tool developed at Motorola, performs the implementations from Verily-AMS to simulators. Third sections concludes the paper by describing by implementation of the EKV model into ADS using the compact model interface provided by Agilent.
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12 citations 107 reads

[ESSCIRC 2015] Low-power analog RF circuit design based on the inversion coefficient

[ref] Enz, Christian; Chalkiadaki, Maria-Anna; Mangla, Anurag, "Low-power analog/RF circuit design based on the inversion coefficient," in ESSCIRC 2015 - 41st , vol., no., pp.202-208, 14-18 Sept. 2015

Abstract: This paper discusses the concept of the inversion coefficient as an essential design parameter that spans the entire range of operating points from weak via moderate to strong inversion, including velocity saturation. Several figures-of-merit based on the inversion coefficient, especially suitable for the design of low-power analog and RF circuits, are presented. These figures-of-merit incorporate the various trade-offs encountered in analog and RF circuit design. The use of the inversion coefficient and the derived figures-of-merit for optimization and design is demonstrated through simple examples. Finally, the simplicity of the inversion coefficient based analytical models is emphasized by their favorable comparison against measurements of a commercial 40-nm bulk CMOS process as well as with simulations using the BSIM6 model.

Keywords: Analytical models, Integrated circuits, Noise, Radio frequency, Silicon, Transconductance, Transistors, BSIM6

URL / doi: 10.1109/ESSCIRC.2015.7313863

Analog CMOS from 5 micrometer to 5 nanometer

 Sansen, W., "1.3 Analog CMOS from 5 micrometer to 5 nanometer," ISSCC 2015 IEEE International , vol., no., pp.1,6, 22-26 Feb. 2015 doi: 10.1109/ISSCC.2015.7062848 

Abstract: In our future, as usual, analog designers will continue to expand their expertise and knowledge in response to changing needs. While devices will change their nature and operate at higher and higher frequencies, their I-V characteristics will remain similar. In the near term, increased speed of MOS circuits, will be reached by operating deeper in weak inversion. Offset and 1/f noise will continue to play a critical role. Thus, in general, it seems that analog expertise is insensitive to technology change.

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