[paper] Boropheneand Metal Interface

Vaishnavi Vishnubhotla, Sanchali Mitra, and Santanu Mahapatraa

First-principles based study of 8-Pmmn boropheneand metal interface

J. Appl. Phys. 134, 034301 (2023); doi: 10.1063/5.0144328

DOI 10.1063/5.0144328

Nano-Scale Device Research Laboratory, Department of Electronic Systems Engineering, 

Indian Institute of Science (IISc) Bangalore, India

Abstract: Borophene, the lightest member of mono-elemental 2D materials family, has attracted much attention due to its intriguing polymorphism. Among many polymorphs, digitally discovered 8-Pmmn stands out owing to its unique tilted-Dirac fermions. However, the property of interfaces between 8-Pmmn and metal substrates has so far remained unexplored, which has critical importance of its application in any electronic devices. Here, with the help of density functional theory, we show that the unique tilted-Dirac property is completely lost when 8-Pmmn borophene is interfaced with common electrode materials such as Au, Ag, and Ti. This is attributed to the high chemical reactivity of borophene as observed from crystal orbital Hamilton population and electron localization function analysis. In an effort to restore the Dirac property, we insert a graphene/hexagonal-boron-nitride (hBN) layer between 8-Pmmn and metal, a technique used in recent experiments for other 2D materials. We show that while the insertion of graphene successfully restores the Dirac nature for all three metals, hBN fails to do so while interfacing with Ti. The quantum chemical insights presented in this work may aid in to access the Dirac properties of 8-Pmmn in experiments.

FIG: (a) Top and side views of 3 × 3 × 1 supercell of 8-Pmmn borophene. The lattice parameters are a = 3.26 Å, b = 4.52 Å, and h = 2.19 Å. The inner and ridge atoms are denoted by blue and green atoms, respectively. (b) Crystal orbital Hamilton population (COHP) analysis and (c) electron localization function (ELF) plot for graphene and 8-Pmmn borophene.

Acknowledgments: The authors acknowledge the Supercomputer Education and Research Center (SERC), Indian Institute of Science (IISc), Bangalore, for CPU- and GPU-based computations. The computational charges were aided by the Mathematical Research Impact Centric Support (MATRICS) scheme of Science and Engineering Research Board (SERB), Government of India, under Grant No. MTR/2019/000047.

[paper] Atomic-scale defects in Si/SiO2 transistors

Stephen J. Moxim1, Fedor V. Sharov1, David R. Hughart2, Gaddi S. Haase2, Colin G. McKay2, and Patrick M. Lenahan1

Atomic-scale defects generated in the early/intermediate stages of dielectric breakdown in Si/SiO2 transistors

Appl. Phys. Lett. 120, 063502 (2022);

DOI:10.1063/5.0077946

   

1 The Pennsylvania State University, USA
2 Sandia National Laboratories, New Mexico, USA

Abstract: Electrically detected magnetic resonance and near-zero-field magnetoresistance measurements were used to study atomic-scale traps generated during high-field gate stressing in Si/SiO2 MOSFETs. The defects observed are almost certainly important to time-dependent dielectric breakdown. The measurements were made with spin-dependent recombination current involving defects at and near the Si/SiO2 boundary. The interface traps observed are Pb0 and Pb1 centers, which are silicon dangling bond defects. The ratio of Pb0/Pb1 is dependent on the gate stressing polarity. Electrically detected magnetic resonance measurements also reveal generation of E′ oxide defects near the Si/SiO2 interface. Near-zero-field magnetoresistance measurements made throughout stressing reveal that the local hyperfine environment of the interface traps changes with stressing time; these changes are almost certainly due to the redistribution of hydrogen near the interface.

FIG: Atomic-scale picture of defect formation and hydrogen motion during the early and intermediate stages of SiO2 degradation and breakdown.

Acknowledgements: This work was supported by the Defense Threat Reduction Agency (DTRA) under Award No. HDTRA1-18-0012. The content of the information does not necessarily reflect the position or the policy of the federal government and no official endorsement should be inferred

[paper] Generalized EKV Charge-based MOSFET Model

A Generalized EKV Charge-based MOSFET Model Including Oxide and Interface Traps

Chun-Min Zhang^a,  Farzan Jazaeri^a,  Giulio Borghello^b,  Serena Mattiazzo^c,  Andrea Baschirotto^d

and Christian Enz^a

Solid-State Electronics

Available online 7 January 2021, 107951

Open Access under a Creative Commons License

DOI: 10.1016/j.sse.2020.107951

a Integrated Circuits Laboratory (ICLAB), École Polytechnique Fédérale de Lausanne (EPFL), Neuchâtel 2000, Switzerland

b Department of Experimental Physics, CERN, Geneva 1211, Switzerland

c Department of Information Engineering, INFN Padova and University of Padova, Padova 35131, Italy

d Microelectronic Group, INFN Milano-Bicocca and University of Milano-Bicocca, Milano 20126, Italy

Abstract: This paper presents a generalized charge-based EKV MOSFET model that includes the effects of trapped charges in the bulk oxide and at the silicon/oxide interface. It is shown that in the presence of oxide- and interface-trapped charges, the mobile charge density can still be linearized but with respect to both the surface potential and the channel voltage. This enables us to derive closed-form expressions for the mobile charge density and the drain current. These simple formulations demonstrate the effects of charge trapping on MOSFET characteristics and crucial device parameters. The proposed charge-based analytical model, including the effect of velocity saturation, is successfully validated through measurements performed on devices from a 28nm bulk CMOS technology. Ultrahigh total ionizing doses up to 1 Grad (SiO2) are applied to generate oxide-trapped charges and activate the passivated interface traps. Despite a small number of parameters, the model is capable of accurately capturing the measurement results over a wide range of device operation from weak to strong inversion. Explicit expressions of device parameters also allow for the extraction of the oxide- and interface-trapped charge density.

Fig: Energy band diagrams illustrating interface charge trapping in bulk n- (a) and pMOSFETs (b) in inversion. The quasi-Fermi level of the minority carriers, 𝐸𝐹𝑛 or 𝐸𝐹𝑝, is split from that of the majority carriers 𝐸𝐹 by the channel voltage 𝑉𝑐ℎ

Acknowledgements: The authors would like to thank the EP-ESE group at CERN, especially Dr. Federico Faccio, for the continuous support in radiation measurements and the interesting discussions about data analysis. This work was supported in part by the Swiss National Science Foundation (SNSF) through the GigaradMOST project under grant number 200021_160185 and in part by the Istituto Nazionale di Fisica Nucleare (INFN) through the ScalTech28 Project.