T. Komawaki, M. Yabuuchi, R. Kishida, J. Furuta, T. Matsumoto and K. Kobayashi
Circuit-level simulation methodology for Random Telegraph Noise by using Verilog-AMS
2017 IEEE ICICDT, Austin, TX, USA, 2017, pp. 1-4.
doi: 10.1109/ICICDT.2017.7993526
Abstract: As device sizes are downscaled to nanometer, Random Telegraph Noise (RTN) becomes dominant. It is indespensable to accurately estimate the effect of RTN. We propose the RTN simulation method for analog circuits. It is based on the charge trapping model. We replicate the RTN-induced threshold voltage fluctuation to attach a variable DC voltage source to the gate of MOSFET by using Verilog-AMS. We confirm that drain current of MOSFETs temporally fluctuates. The fluctuations of RTN are different for each MOSFET. Our proposed method can be applied to estimate the temporal impact of RTN including multiple transistors. We can successfully replicate RTN-induced frequency fluctuations in 3-stage ring oscillators as similar as the measurement results [read more...]
