LETI Compact Modeling Links

LETI compact modeling links points to the Workshops and Conferences:

MOS-AK (Modeling of Systems and Parameter Extraction Working Group)
S3S (IEEE SOI-3D Subthreshold Microelectronics Technology Unified Conference)

IEDM (IEEE International Electron Devices Meeting)
VLSI  (29th International Conference on VLSI Design)
SISPAD (Simulation of Semiconductor Processes and Devices)

[read more...]

[mos-ak] [2nd Announcement and Call for Papers] MOS-AK ESSDERC/ESSCIRC Workshop; Lausanne September 12, 2016

 MOS-AK ESSDERC/ESSCIRC Workshop  

  Lausanne September 12, 2016 
   2nd Announcement and Call for Papers  

 Together with International MOS-AK Board of R&D Advisers: Larry Nagel, Omega Enterprises Consulting (USA), Andrei Vladimirescu, UCB (USA); ISEP (FR) and local workshop coordinator Jean-Michel Sallese, EPFL (CH) as well as all the Extended MOS-AK TPC Committee, we have pleasure to invite to the 14th consecutive MOS-AK ESSDERC/ESSCIRC Workshop which will be held at Swisstech Convention Centre in Lausanne on September 12, 2016. Planned MOS-AK workshop is organized with aims to strengthen a network and discussion forum among experts in the field, enhance open platform for information exchange related to compact/SPICE modeling and Verilog-A standardization, bring people in the compact modeling field together, as well as obtain feedback from technology developers, circuit designers, and CAD/EDA tool developers and vendors. 

Important Dates:

• Call for Papers - June 2016
• 2nd Announcement - July 2016
• Final Workshop Program - August 2016
• MOS-AK Workshop - Sept.12 2016

Venue:

Swisstech Convention Centre EPFL                                        
Route Louis-Favre 2
CH-1024 Ecublens

Topics to be covered include the following among other related to the compact/SPICE modeling :

• Advances in semiconductor technologies and processing
• Compact Modeling (CM) of the electron devices
• Verilog-A language for CM standardization
• New CM techniques and extraction software
• Open Source TCAD/EDA modeling and simulation
• CM of passive, active, sensors and actuators
• Emerging Devices, TFT, CMOS and SOI-based memory cells
• Microwave, RF device modeling, high voltage device modeling
• Nanoscale CMOS devices and circuits
• Technology R&D, DFY, DFT and reliability/ageing IC Designs
• Foundry/Fabless Interface Strategies

Speakers: tentative list of MOS-AK Experts:

• Marco Bellini, ABB (CH)
• Mike Brinson, LondonMet, (UK)
• Matthias Bucher, TUC (GR)
• Mansun Chan, UST (HK)
• James Greer, ASCENT, Tyndall (IE)
• Benjamin Iniguez, URV (SP)
• Alexander Kloes, THM (D)
• Muhammad Nawaz, ABB (SE)
• Denis Rideau, ST (F)
• Jean-Michel Sallese, EPFL (CH)
• Andrei Vladimirescu, UCB (USA); ISEP (FR); Keynote
• Lining Zhang, UST (HK)

Online MOS-AK Abstract Submission:
Prospective authors should submit an abstract to abstracts@mos-ak.org

Online Workshop Registration:

http://esscirc-essderc2016.epfl.ch/registration
(any related inquiries can be sent to register@mos-ak.org)

Postworkshop Publications:
Selected best MOS-AK technical presentation will be recommended for further publication in a special issue of the International Journal of High Speed Electronics and Systems

Extended MOS-AK Committee

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IEDM: Modeling and Simulation – Compact Modeling

 IEEE International Electron Devices Meeting (IEDM) is the world’s preeminent forum for reporting technological breakthroughs in the areas of semiconductor and electronic device technology, design, manufacturing, physics, and modeling. IEDM is the flagship conference for nanometer-scale CMOS transistor technology, advanced memory, displays, sensors, MEMS devices, novel quantum and nano-scale devices and phenomenology, optoelectronics, devices for power and energy harvesting, high-speed devices, as well as process technology and device modeling and simulation. This year IEDM technical program also includes a series of the compact modeling papers:

[9.6] GaNFET Compact Model for Linking Device Physics, High Voltage Circuit Design and Technology Optimization, U. Radhakrishna, S. Lim, P. Choi, T. Palacios, and D.A Antoniadis, Massachusetts Institute of Technology
[28.1] Transport Mechanism in sub 100C Processed High Mobility Polycrystalline ZnO Transparent Thin Film Transistors, P.B. Pillai, and M.M. De Souza, University of Sheffield
[28.2] Physical-based Analytical Model of flexible a-IGZO TFTs Accounting for Both Charge Injection and Transport, M. Ghittorelli, F. Torricelli, J.L. Van Der Steen*, C. Garripoli**, A. Tripathi*, G. Gelinck*, E. Cantatore**, Z. Kovacs-Vajna, University of Brescia, *Holst Centre, TNO, **Eindhoven University of Technology
[28.3] Predictive Compact Modeling of Random Variations in FinFET Technology for 16/14nm Node and Beyond, X. Jiang, X. Wang*, R. Wang, B. Cheng**, A. Asenov*, and R. Huang, Peking University, *University of Glasgow, **Gold Standard Simulations (GSS) Ltd.
[28.4] A New Surface Potential Based Physical Compact Model for GFET in RF Applications, L. Wang, S. Peng, Z. Zong, L. Li, W. Wang, G. Xu, N. Lu, Z. Ji, and M. Liu, Chinese Academy of Sciences
[28.5] Physics-based Compact Modeling Framework for State-of-the-Art and Emerging STT-MRAM Technology, N. Xu, J. Wang, Y. Lu, H.-H. Park, B. Fu, R. Chen, W. Choi, D. Apalkov, S. Lee*, S. Ahn*, Y. Kim*, Y. Nishizawa**, K.-H. Lee, Y. Park, Samsung Semiconductor Inc, *Samsung Electronics, **Samsung R&D Institute Japan
[28.6] Physics-based Compact Modeling of Charge Transport in Nanoscale Electronic Devices (Invited), S. Rakheja, and D. Antoniadis*, New York University, *Massachusetts Institute of Technology

The compact/SPICE modeling and its Verilog-A standardization will be also discussed at two following engineering events organized by MOS-AK Group and the CMC which are collocated with the IEDM in Washington DC in December, later this year.

[online MOS-AK and CMC registration]

• MOS-AK Workshop in Washington DC (Dec.9) 
• http://www.mos-ak.org/washington_dc_2015/
• CMC Meeting at Sheraton Suites Old Town Alexandria (Dec.10-11)
• https://www.si2.org/openeda.si2.org/4Q_2015_CMC_Meeting.php

MOS-AK article reached 400 reads

 MOS-AK article reached 400 reads

• 

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   Open-Source Circuit Simulation Tools for RF Compact Semiconductor Device Modelling

  September 2014 · International Journal of Numerical Modelling Electronic Networks Devices an...

   Wladek Grabinski · Mike Brinson · Paolo Nenzi · Francesco Lannutti· Nikolaos Makris · Angelos Antonopoulos · Matthias Bucher 

  Abstract: MOS-Modelle und Parameterextraktion Arbeitskreis (MOS-AK) is a European, independent compact modelling forum created by a group of engineers, researchers and compact modelling engineers...

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  1 CITATION 401 READS

ESSDERC ESSCIRC in Graz (A)

 ESSDERC 2015: 45th European Solid-State Device Conference

 ESSCIRC 2015: 41th European Solid-State Circuits Conference

 September 14-18, 2015 - Graz, Austria

The aim of ESSDERC and ESSCIRC is to provide an annual European forum for the presentation and discussion of recent advances in solid-state devices and circuits. The increasing level of integration for system-on-chip design made available by advances in silicon technology is, more than ever before, calling for a deeper interaction among technologists, device experts, IC designers, and system designers. While keeping separate Technical Program Committees, ESSCIRC and ESSDERC are governed by a common Steering Committee and share Plenary Keynote Presentations and Joint Sessions bridging both communities. Attendees registered for either conference are encouraged to attend any of the scheduled parallel sessions, regardless to which conference they belong.

Read more:

• Program at a glance (Sept. 14 to 18, 2015 including Tutorials and Workshops)
• Program folder

[MOS-AK/DATE 2015 Workshop] CEA-Leti's predictive model takes FDSOI further

 CEA-Leti's predictive model takes FDSOI further 

During DATE 2015’s MOS-AK Workshop, CEA-Leti presented the newest version of its advanced compact model for ultra-thin body and buried oxide fully depleted SOI (UTBB-FDSOI) technology.

Fully Depleted Silicon On Insulator (FDSOI) is a planar process technology that relies on two primary innovations. First, an ultra-thin layer of insulator, called the buried oxide, is positioned on top of the base silicon.

Then, a very thin silicon film implements the transistor channel. Thanks to its thinness, there is no need to dope the channel, thus making the transistor fully depleted. The combination of these two innovations is called “ultra-thin body and buried oxide Fully Depleted SOI” or UTBB-FDSOI.

Back in 2013, CEA-Leti had deployed a first compact model, but working in close cooperation with STMicroelectronics, the research lab understood that more subtle back gate channelling effects had to be addressed to fully exploit the benefits of UTBB-FDSOI and to explore the transistors’ behaviour in more details.

New analytical equations were written from scratch for the Leti-UTSOI2.1 compact model, improving on the predictability and accuracy capabilities of the previous version, Leti-UTSOI2.

To date, other models from the University of Hiroshima, and from the University of Berkeley fail to account for inversion effects at the back interface, when a strong forward back bias (FBB) is applied, told us Thierry Poiroux, Leti research engineer and model co-developer.

More specifically, the French lab used a unique analytical resolution scheme for the calculation of surface potentials at both interfaces of the transistor body, offering a refined description of narrow-channel effects, with an improved accuracy of moderate inversion regime and gate tunnelling current modelling.

Because the model is analytical, it is much faster than any numerical simulation. It is now available in all major SPICE and Fast SPICE simulators through licences with EDA vendors and will allow fabless companies and IC designers to virtually explore different UTBB-FDSOI parameters within a given foundry process node. The new model can also be used by foundries and fabless companies to perform a predictive analysis of future nodes to come, in order to orient their ongoing process optimization.

for more information visit CEA-Leti at www.leti.fr

ESSDERC/ESSCIRC 2014 - Full conference program is now available

The technical program, tutorial program, and workshop program of ESSDERC/ESSCIRC 2014
are now available at  ESSDERC/ESSCIRC 2014  website: http://www.esscirc-essderc2014.org 

Please remember to register to the conference and book a hotel room at before June 20, after 
which we cannot guarantee that you will find a hotel room at our rebated prices.

The event is technically co-sponsored by the
    IEEE Electron Device Society,
    IEEE Solid-State Circuit Society
    IEEE Circuits and Systems Society

We hope to see you in Venice

Best Regards  Gaudenzio Meneghesso
ESSDERC/ESSCIRC 2014  General Chair

Roberto Bez and Paolo Pavan
ESSDERC 2014 TPC Chairs

Pietro Andreani and Andrea Bevilacqua 
ESSCIRC 2014 TPC Chairs


JOINT PLENARY TALKS 
Scott DeBoer, Micron, ID, USA, A Semiconductor Memory Manufacturing and Development Perspective
Thomas H. Lee, Stanford University, CA, USA Terahertz Electronics: The Last Frontier 
Fabio Marchiò, STMicroelectronics, Italy, Automotive Electronics: Application & Technology Megatrends
Walter Snoeys, CERN, Switzerland, How Chips Helped Discover the Higgs Boson at CERN
An Steegen, IMEC, Belgium, Logic Scaling Beyond 10nm, a Power-Performance-Area-Cost Trade-off 
Sehat Sutardja, Marvell Semiconductor, CA, USA Tremendous Benefits of Moore’s Law Have Yet to Come

ESSCIRC PLENARY TALKS
Hooman Darabi, Broadcom Corporation, CA, USA Blocker Tolerant Software Defined Receivers

Un-Ku Moon, Oregon State University, OR, USA Emerging ADCs
Kathleen Philips, IMEC-Holst Centre, The Netherlands Ultra-Low Power Short Range Radios

ESSDERC PLENARY TALKS
Umesh Mishra, UCSB and TRanphorm, CA, USA,  GaN-based solutions from KHz to THz 

Eric Pop, Stanford University, CA, USA, Energy Efficiency and Conversion in 1D and 2D Electronics
Takao Someya, University of Tokyo, Japan Bionic Skins Using Flexible Organic Devices

ESSCIRC TUTORIALS

Power Management for SoCs (Full Day), Organizer: Christoph Sandner, Infineon, Austria
High Performance Amplifiers (Half Day), Organizer: Angelo Nagari, STMicroelectronics, France
Phase Noise: from Fundamentals to Circuit Aspects (Half Day) Organizer: Christian Enz, EPFL, Switzerland

ESSDERC TUTORIALS
CMOS Technology at the nm Scale Era (Full Day) Organizer: Maud Vinet, CEA LETI, France

RRAM: from Technology to Applications (Half Day) Organizer: Bogdan Govoreanu, IMEC, Belgium 
3D: from Technology to Applications (Half Day) Organizer: Pascal Vivet, CEA LETI, France

ESSDERC/ESSCIRC Workshops
Beyond-CMOS for advanced More Moore and More than Moore applications 
Organizers: Francis Balestra and Enrico Sangiorgi, Sinano Institute - Grenoble INP/CNRS, France
MOS-AK: Over Two Decades of Enabling Compact Modeling R&D Exchange   
Organizer: Wladek Grabinski, MOS-AK Group (EU),
Status of the GaN and SiC based device development   
Organizer: Enrico Zanoni, University of Padova, DEI, Italy
THz-Workshop: Millimeter- and Sub-Millimeter-Wave circuit design and characterization   
Organizer: Thomas Zimmer, University Bordeaux, France
Marie Curie ATWC   
Organizer: Rinaldo Castello, University of Pavia and Marvell, Italy

Lots of Foundries and Fabless Companies do exist - what about standards for their interface?

DATE 2010 ET-P3 PANEL SESSION

Date: Thu, 2010-03-11; Time: 12:45-13:45
Room: Exhibition Theatre, Ground Floor

Organizers: Manfred Dietrich, Fraunhofer IIS/EAS, and Rene Schueffny, TU Dresden

Companies like Broadcom and Nvidia have shown that the Fabless model conquers the semiconductor market. Today all IDM’s use foundries as second source or use it as part of their volume production Because of the high cost of new manufacturing facilities IDM’s become Fablight and concentrate with their production on highly sophisticated processes. How is it possible to handle even more complex circuits if their processes cannot any more be deeply influenced by the internal design team? Today the value chain of the semiconductor market isolates and dominates more and more the vertical companies like EDA, Design house, Fabless, IP provider, Foundry Test & Packaging. Do we have already enough standards or do we need more and where do we need more standards and how can we make it happen? Who will be the driver or who should be the driver? This panel should offer some answers or even create more questions! It is fact - Fabless companies will have more and more impact in the whole IC logic market and Foundries increase their market share every year! Is it time for standards? [more]

Download DATE 2010 Conference Programme (PDF - 3 MB)

MOS-AK/GSA Workshop: 2-3 April 2009 at IHP in Frankfurt /Oder

MOS-AK/GSA Workshop: 2-3 April 2009 at IHP in Frankfurt /Oder

• Final program (COMON Project Meeting & MOS-AK Workshop)
  
• Free on-line registration
• Driving directions

MOS-AK/GSA merge

In January 2009, GSA merged its efforts with MOS-AK, a well-known industry compact modeling volunteer group primarily focused in Europe, to re-activate its Modeling Working Group. This working group will help to create a smooth compact modeling interface between the technology (CMOS fabrication) and the IC design. For more information on this working group, contact Chelsea Boone or Wladek Grabinski

visit: EDA/Design Working Groups