Isaac Bruce, Michael Sekyere, Ruohan Yang, Saeid Karimpour, Colin C. McAndrew, Degang Chen
Gradient Minimization in Layout Patterns for Analog Circuits
Circuits, Systems, and Signal Processing. 1-22.
DOI: 10.1007/s00034-025-03158-x
Abstract: In this paper, we present an algorithm to generate the layout of a pair of devices A and B for a given matching ratio r and total unit cell count N that minimizes the mismatch due to systematic gradient effects. The algorithm relies on simple reflections and rotations of an initial optimized pattern across 4 quadrants. The approach cancels all odd-order systematic gradients and minimizes 2nd order systematic gradients. The method can easily be extended to cancel higher-order even gradient effects. The validity of the proposed algorithm is demonstrated via numerical simulations. Additionally, an electrothermal simulation of a set of layouts is run to further validate the proposed layout generation scheme.
FIG: Layout of circuit design with heat sources and current sources
for the optimal transistor array pattern.
