[paper] artificial synapse

Md. Hasan Raza Ansari, Udaya Mohanan Kannan, and Nazek El-Atab

Silicon Nanowire Charge Trapping Memory for Energy-Efficient Neuromorphic Computing

IEEE Transactions on Nanotechnology (2023)

DOI 10.1109/TNANO.2023.3296673

SAMA Labs, CEMSE Division, KAUST, Thuwal 23955-6900, Saudi Arabia

Department of Electronic Engineering, Gachon University, Seongnam 13120, Korea

Abstract: This work highlights the utilization of the floating body effect and charge-trapping/de-trapping phenomenon of a Silicon-nanowire (Si-nanowire) charge-trapping memory for an artificial synapse of neuromorphic computing application. Charge trapping/de-trapping in the nitride layer characterizes the long-term potentiation (LTP)/depression (LTD). The accumulation of holes in the potential well achieves short-term potentiation (STP) and controls the transition from STP to LTP. Also, the transition from STP to LTP is analyzed through gate length scaling and high-κ material (Al2O3) for blocking oxide. Furthermore, the conductance values of the device are utilized for system-level simulation. System-level hardware parameters of a convolutional neural network (CNN) for inference applications are evaluated and compared to a static random-access memory (SRAM) device and charge-trapping memory. The results confirm that the Si-nanowire transistor with better gate controllability has a high retention time for LTP states, consumes low power, and archives better accuracy (91.27%). These results make the device suitable for low-power neuromorphic applications.

FIG: Schematic representation of biological and Si-nanowire charge trapping memory as an artificial synapse

[paper] TMD FETs

Ahmed Mounir^a, Benjamin Iñiguez^a, François Lime^a, Alexander Kloes^b

Theresia Knobloch^c, Tibor Grasser^c

Compact I-V model for back-gated and double-gated TMD FETs

Solid-State Electronics (2023): 108702

DOI: 10.1016/j.sse.2023.108702

a Rovira I Virgili University, Tarragona, Spain
b University of Applied Sciences, Giessen, Germany
c TU Wien, Vienna, Austria

Abstract: A physics-based analytical DC compact model for double and single gate TMD FETs is presented. The model is developed by calculating the charge density inside the 2D layer which is expressed in terms of the Lambert W function that recently has become the standard in SPICE simulators. The current is then calculated in terms of the charge densities at the drain and source ends of the channel. We validate our model against measurement data for different device structures. A superlinear current increase above certain gate voltage has been observed in some MoS2 FET devices, where we present a new mobility model to account for the observed phenomena. Despite the simplicity of the model, it shows very good agreement with the experimental data.

Fig : 2D schematic structure for 2D TMD FETs: (a) a double gated monolayer MoS2 FET. 

(b) a double gated monolayer WSe2 FET. (c)  single back-gated multilayer MoS2 FET. 

(d) single back-gated monolayer FET.

[paper] Bionic Neural Probe

Yu Zhou, Huiran Yang, Xueying Wang, Heng Yang, Ke Sun, Zhitao Zhou, Liuyang Sun, Jianlong Zhao, Tiger H. Tao and Xiaoling Wei

A mosquito mouthpart-like bionic neural probe

Microsystems & Nanoengineering volume 9, Article number: 88 (2023)

DOI: 10.1038/s41378-023-00565-5

Abstract: Organic electronics can be biocompatible and conformable, enhancing the ability to interface with tissue. However, the limitations of speed and integration have, thus far, necessitated reliance on silicon-based technologies for advanced processing, data transmission and device powering. Here we create a stand-alone, conformable, fully organic bioelectronic device capable of realizing these functions. This device, vertical internal ion-gated organic electrochemical transistor (vIGT), is based on a transistor architecture that incorporates a vertical channel and a miniaturized hydration access conduit to enable megahertz-signal-range operation within densely packed integrated arrays in the absence of crosstalk. These transistors demonstrated long-term stability in physiologic media, and were used to generate high-performance integrated circuits. We leveraged the high-speed and low-voltage operation of vertical internal ion-gated organic electrochemical transistors to develop alternating-current-powered conformable circuitry to acquire and wirelessly communicate signals. The resultant stand-alone device was implanted in freely moving rodents to acquire, process and transmit neurophysiologic brain signals. Such fully organic devices have the potential to expand the utility and accessibility of bioelectronics to a wide range of clinical and societal applications.

FIG: Multifunctional biomimetic neural probe system, with multichannel flexible electrode array and high sensitivity sensor array. 

[chapter] GAA Transistors

Srivastava, Shobhit, and Abhishek Acharya

Challenges and future scope of gate-all-around (GAA) transistors

in "Device Circuit Co-Design Issues in FETs"; 

Shubham Tayal et al. (Editors)

231 CRC Press, 22 Aug 2023 - Technology & Engineering

Introduction: No doubt, FinFET technology is the slogger of today's semiconductor world. But as demand for further scaling with a desire for ultra-low-power and high-speed applications results in undesired short-channel effects, a new transistor is required. This is where gate-all-around (GAA) devices come into being. The GAA structure helps to mitigate unwanted short-channel effects by enhancing channel controllability. In GAAFETS, the channel surrounds all of its sides through a high-K and interfacial oxide layer. Thanks to science and technological innovation, the GAAFET family brings together different transistors and their competitive benefits. This chapter tries to answer why and how 3D devices emerge. In addition to the limitation of FinFET (a 3D device, gate surrounded by three sides), it further talks about the scope and challenges of different competitive GAAFET members (nanowire FET, nanosheet FET, junctionless nanosheet FET, complementary PET, and forksheet FET) of the GAAFET family. It is worth mentioning that a smaller benefit of the device performance exerts a massive performance enhancement on circuit-level applications. However, the advantages of device enhancement concurrently exaggerate the limitation of devices at circuit-level applications. So, an elaborated idea of GAAFETs holding the benefits and challenges at the circuit is also discussed here.

FIG: Structural evolution of transistors from planar to 3D forksheet FET technology

[paper] Printed OTFTs

Non-Quasi-Static modeling of printed OTFTs

Antonio Valletta^1,2, Matteo Rapisarda^1,2, Mattia Scagliotti¹, Guglielmo Fortunato¹, Luigi Mariucci^1,2, Andrea Fabbri², Paolo Branchini² and Sabrina Calvi^1,2,3,4

IEEE J-EDS, 2023, Jul 7

 
1 CNR - Institute for Microelectronics and Microsystems (IMM), via del Fosso del Cavaliere, 100, 00133 Rome, Italy
2 INFN, Sezione di RomaTre, via della Vasca Navale, 00146 Rome, Italy
3 CNR-SPIN UoS di Napoli, Università degli Studi di Napoli Federico II, Dipartimento di Fisica, piazzale Tecchio, 80, 80125, Napoli, Italy
4 Department of Physics University of “Tor Vergata”, via della Ricerca Scientifica 1, 00133, Rome, Italy

Abstract: A non-quasi-static compact model well suited for the simulation of the electrical behavior of printed organic thin-film transistors (OTFTs) is proposed and validated. The model is based on the discretization of the current continuity equation by using a spline collocation approach, while the electrical transport in the organic semiconductor is described by the variable range hopping theory. The model accounts for the presence of parasitic regions that are often found in the layouts of printed OTFTs due to large process tolerances. The model has been implemented in the Verilog-A language and has been validated by a comparison with the capacitance vs. voltage (small signal) characteristics of the devices and measurements made on OTFT-based common-source amplifiers (large signal). A comparison with a quasi-static version of the model is reported. 

FIG: Typical device layout (in scale) of the printed OTFTs and its DC (static) characterization: transfer and output characteristics of an L=100µm W=400µm device measured after light exposure

Aknowledgements: This work has been funded by the Italian National Institute of Nuclear Physics – INFN -5th commission, under the “FIRE” project (2019-2022) and from INFN-CNR national project (PREMIALE 2012) EOS “Organic Electronics for Innovative research instrumentation”.