Showing posts with label double-gate MOSFET. Show all posts
Showing posts with label double-gate MOSFET. Show all posts

Aug 30, 2017

[paper] Surface Potential Equation for Low Effective Mass Channel Common Double-Gate MOSFET

Ananda Sankar Chakraborty and Santanu Mahapatra, Senior Member, IEEE
in IEEE Transactions on Electron Devices
vol. 64, no. 4, pp. 1519-1527, April 2017
doi: 10.1109/TED.2017.2661798

Abstract: Formulation of accurate yet computationally efficient surface potential equation (SPE) is the fundamental step toward developing compact models for low effective mass channel quantum well MOSFETs. In this paper, we propose a new SPE for such devices considering multisubband electron occupancy and oxide thickness asymmetry. Unlike the previous attempts, here, we adopt purely physical modeling approaches (such as without mixing the solutions from finite and infinite potential wells or using any empirical model parameter), while preserving the mathematical complexity almost at the same level. Gate capacitances calculated from the proposed SPE are shown to be in good agreement with numerical device simulation for wide range of channel thickness, effective mass, oxide thickness asymmetry, and bias voltages [read more...]
FIG: Total gate capacitance per unit width Cgg (Vg) for 7-nm-thick device with 100% asymmetry in front and back oxide thicknesses. nmax = 2. Line = model. Symbol = TCAD

Aug 3, 2017

[paper] On the Physical Behavior of Cryogenic IV and III-V Schottky Barrier MOSFET Devices

On the Physical Behavior of Cryogenic IV and III–V Schottky Barrier MOSFET Devices
Mike Schwarz, Member, IEEE, Laurie E. Calvet, Member, IEEE, John P. Snyder, Member, IEEE, Tillmann Krauss, Udo Schwalke, Senior Member, IEEE, and Alexander Kloes, Senior Member, IEEE
in IEEE TED , vol.PP, no.99, pp.1-8
doi: 10.1109/TED.2017.2726899

Abstract: The physical influence of temperature down to the cryogenic regime is analyzed in a comprehensive study and the comparison of IV and III-V Schottky barrier (SB) double-gate MOSFETs. The exploration is done using the Synopsys TCAD Sentaurus device simulator and first benchmarked with experimental data. The important device physics of both SB-MOSFETs and conventional MOSFETs are reviewed. The impact of temperature on device performance down to the liquid-nitrogen regime is then explored. We find reduced drive currents in SB-MOSFETs fabricated on small effective mass materials and that SB lowering can significantly improve SB-MOSFETs, especially at low temperatures [read more...]

This article has been accepted for inclusion in a future issue of this journal. Content is final as presented, with the exception of pagination