Analog IC Design Using Open Source Tools and IHP-Open-PDK
at TU Poznan prior to MIXDES 2026
June 24, 2026
<https://www.mixdes.org/Mixdes3/tekst/view/openpdk-analog>
It is interactive demonstration workshop format with the possibility to work at stations prepared by the organizer. Personal computers are not required; however, participants may use their own laptops if they wish. with the possibility to work at stations prepared by the organizer. Personal computers are not required; however, participants may use their own laptops if they wish. The workshop is embedded into the IEEE EDS FET100 Anniversary celebration. Our workshop's expected outcome is successful integrated circuits (IC) design, submission, and fabrication (tapeout) of participants created ICs. To recognize excellence in hands‑on integrated‑circuit design, the IEEE EDS will present Student Open Silicon Prizes for outstanding student in IC design. The IEEE Electron Devices Society (EDS), together with other IEEE societies, covers complete flow from the electron devices to IC designs thru CAD/EDA software support:
- Devices (EDS): semiconductor physics, fabrication technologies
- Circuits (SSCS, CASS): analog, digital, mixed-signal, system-level design
- Design Automation (CEDA): CAD tools, verification, open-source flows
AGENDA
| Start | End | Topic |
|---|---|---|
| 8:00 | 8:30 | Participant registration, organizational introduction |
| 8:30 | 9:00 | FET100 Inauguration Speech¹: Prof. K. Detka, IEEE EDS Poland |
| 9:00 | 10:30 |
OpenSilicon DIY Integrated Circuits²: Dr. Krzysztof Herman, IHP (D) Introduction to analog design in an open-source environment (Tools overview: Xschem, Ngspice, IHP-Open-PDK, workflow basics) |
| 10:30 | 10:45 | Coffee break |
| 10:45 | 12:30 | Analog schematic design in Xschem best practices, parameterization, DC, AC, and transient simulations (live demo) |
| 12:30 | 13:30 | FET100 Luncheon Talk³: W. Grabinski, IEEE EDS R8 Chair |
| 13:30 | 15:00 | Design of a sample analog circuit operation analysis, Monte Carlo simulations, mismatch analysis, parameter verification (live demo) |
| 15:00 | 15:15 | Coffee break |
| 15:15 | 17:00 | Introduction to layout in KLayout, analog design principles (matching, symmetry, noise minimization), PyCells mask design automation (live demo) |
| 17:00 | 18:00 | Complete design flow: from schematic to verification (LVS/DRC process overview), fillers, chip finishing, sign-off (live demo) |
| 18:00 | 18:30 | Q&A session, workshop summary |
| 18:30 | >> | FET100 Celebration Appero |
Workshop Tutors:
Dr. Krzysztof Herman, IHP (D); Organizer and Technical Expert Lead
Dr. Wladek Grabinski, IEEE EDS; Technical Assistant
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