[paper] TFT for Mixed Signal and Analog Computation

Eva Bestelink, Olivier de Sagazan, Lea Motte, Max Bateson, Benedikt Schultes, S. Ravi P. Silva,

and Radu A. Sporea

Versatile Thin‐Film Transistor with Independent Control of Charge Injection and Transport

for Mixed Signal and Analog Computation

Adv. Intell. Syst.. (2020) pp.1-9, DOI:10.1002/aisy.202000199 

Abstract: New materials and optimized fabrication techniques have led to steady evolution in large area electronics, yet significant advances come only with new approaches to fundamental device design. The multimodal thin-film transistor introduced here offers broad functionality resulting from separate control of charge injection and transport, essentially using distinct regions of the active material layer for two complementary device functions, and is material agnostic. The initial implementation uses mature processes to focus on the device’s fundamental benefits. A tenfold increase in switching speed, linear input–output dependence, and tolerance to process variations enable low-distortion amplifiers and signal converters with reduced complexity. Floating gate designs eliminate deleterious drain voltage coupling for superior analog memory or computing. This versatile device introduces major new opportunities for thin-film technologies, including compact circuits for integrated processing at the edge and energy-efficient analog computation.

Figure: Outcomes of separating control for injection and conduction shown via TCAD simulation. a) MMT transient response is much faster than conventional contact-controlled TFTs

b) A MMT with multiple, appropriately sized CG1 gates can function as a digital-to-analog converter (DAC) with CG2 providing an enabling, sampleand-hold (S/H) function. 

Acknowledgements: E.B. and R.A.S. contributed equally to this work. This work was partly supported through EPSRC grants EP/R511791/1 and EP/R028559/1 and Research Fellowship 10216/110 from the Royal Academy of Engineering of Great Britain. Device fabrication had been performed on the NanoRennes platform. The authors thank Dr. Brice Le Borgne for initial liaison and process discussions, Prof. John M. Shannon for on-going advisory meetings, Prof. Craig Underwood for reviewing the manuscript, Dr. David Cox and Mr. Mateus Gallucci Masteghin for assistance with the SEM images.

IEEE Germany EDS Chapter Elections

The IEEE Germany EDS Chapter has elected new ExCom members for the term 2020/2021. An exciting new leadership team has been built to establish EDS activities in Germany.

The new ExCom:

• Chair: Mike Schwarz (TH Mittelhessen)
• Vice Chair: Joachim Burghartz (Universität Stuttgart, IMS Chips)
• Treasurer: Manfred Berroth (Universität Stuttgart)
• Secretary: Sevda Abadpour (Karlsruhe Institute of Technology)

Further information is available online https://r8.ieee.org/germany-eds

[paper] Local Variability Evaluation on Effective Channel Length

Juan Pablo Martinez Brito, Graduate Student Member, IEEE, 

and Sergio Bampi, Senior Member, IEEE

Local Variability Evaluation on Effective Channel Length

Extracted with Shift-and-Ratio Method

IEEE TED, vol. 67, no. 11, pp. 4662-4666, Nov. 2020

doi: 10.1109/TED.2020.3017178

Abstract: In this study, the local variation of the effective channel reduction parameter (ΔL=Lm−Leff) of a MOSFET is extracted by means of the traditional shift-and-ratio (SAR) method. ΔL is then correlated with the threshold voltage difference (ΔVTH) between the device under test (DUT) and the reference device. It is demonstrated that there exists an optimal VG range for extracting reliable values of L through the SAR method. Statistical data analysis shows that for R≈ (Llong/Lshort)≈25, better results are achieved since the value of σ(ΔL) varies typically as the reciprocal 1/√ W. The test structure used in this work is a Kelvin-based 2-D addressable MOSFET matrix implemented in 180-nm bulk CMOS technology. The sample space is of 2304 devices divided into nine subgroups of 256 same size closely placed nMOSFETs.

Fig: (a) Full circuit micrograph (b) MOSFET Matrix structure (c) Zoomed-in view at DUTs 

Acknowledgment: The authors would like to thank and acknowledge the Brazilian public company CEITEC S.A. Semiconductors for the measurement infrastructure, the CAD Support Center (NSCAD) at Federal University of Rio Grande do Sul (UFRGS) for electronic design automation (EDA) support, and Silterra Inc. for the silicon prototyping services.

ASCENT project

Applications and Systems-driven Center for Energy-Efficient integrated Nano Technologies

The Mission of the ASCENT Center is to transcend the current limitations of high-performance transistors confined to a single planar layer of integrated circuit by pioneering vertical monolithic integration of multiple interleaved layers of logic and memory, by demonstrating beyond-CMOS device concepts that combine processing and memory functions, heterogeneously integrating functionally diverse nano-components into integrated microsystems and by demonstrating in-memory compute kernels to accelerate future data-intensive at-scale cognitive workloads.

Researchers at ASCENT pursue four areas of technology including three-dimensional integration of device technologies beyond a single planar layer (vertical CMOS); spin-based device concepts that combine processing and memory functions (beyond CMOS); heterogeneous integration of functionally diverse nano-components into integrated microsystems (heterogeneous integration fabric); and hardware accelerators for data intensive cognitive workloads (merged logic-memory fabric).

ASCENT is one of six research centers funded by the SRC’s Joint University Microelectronics Program (JUMP), which represents a consortium of industrial participants and the Defense Advanced Research Projects Agency (DARPA). Information about the SRC can be found at https://www.src.org/.

ASCENT is a collaboration of the following Universities:

Congratulations to Prof. Robert W. Dutton

The 2020 IEEE EDS Celebrated Member and Esteemed EDS Alumni

Dr. Dutton received his degrees from the University of California, Berkeley, and currently instructs electrical engineering at Stanford University. Current members of EDS take pride in the Celebrated Members' accomplishments, drawing from their achievements as inspiration to advance and achieve success in various fields. The award presentation will be held virtually during the 2020 IEDM in December [read more...]

ROBERT W. DUTTON

Robert W. Dutton received the B.S., M.S., and Ph.D. in Electrical Engineering degrees from the University of California, Berkeley, in 1966, 1967, and 1970, respectively. 

He is currently Robert and Barbara Kleist Professor of Electrical Engineering at Stanford University, and Associate Chair for Undergraduate Education. He has held summer staff positions at Fairchild, Bell Telephone Laboratories, Hewlett‐Packard, IBM Research, and Matsushita during 1967, 1973, 1975, 1977, and 1988 respectively. His research interests focus on integrated circuit process, device, and circuit technologies, especially the use of computer‐aided design (CAD) and parallel computational methods. He has published more than 200 journal articles and graduated more than four dozen doctorate students. 

Dr. Dutton was Editor of the IEEE Transactions on Computer Aided Design from 1984 to 1986, the winner of the 1987 IEEE J. J. Ebers Award, 1988 Guggenheim Fellowship to study in Japan, elected to the National Academy of Engineering in 1991, 1996 Jack A. Morton Award, 2000 C&C Prize Japan, University Researcher Award, Semiconductor Industry Association (2000), Phil Kaufman Award, Electronic Design Automation Consortium (2006), and 2014 Bass University Fellow in Undergraduate Education Program, Stanford University.