ASCENT project

Applications and Systems-driven Center for Energy-Efficient integrated Nano Technologies

The Mission of the ASCENT Center is to transcend the current limitations of high-performance transistors confined to a single planar layer of integrated circuit by pioneering vertical monolithic integration of multiple interleaved layers of logic and memory, by demonstrating beyond-CMOS device concepts that combine processing and memory functions, heterogeneously integrating functionally diverse nano-components into integrated microsystems and by demonstrating in-memory compute kernels to accelerate future data-intensive at-scale cognitive workloads.

Researchers at ASCENT pursue four areas of technology including three-dimensional integration of device technologies beyond a single planar layer (vertical CMOS); spin-based device concepts that combine processing and memory functions (beyond CMOS); heterogeneous integration of functionally diverse nano-components into integrated microsystems (heterogeneous integration fabric); and hardware accelerators for data intensive cognitive workloads (merged logic-memory fabric).

ASCENT is one of six research centers funded by the SRC’s Joint University Microelectronics Program (JUMP), which represents a consortium of industrial participants and the Defense Advanced Research Projects Agency (DARPA). Information about the SRC can be found at https://www.src.org/.

ASCENT is a collaboration of the following Universities:

[paper] Power Side-Channel Attacks in NCFET

Knechtel, Johann, Satwik Patnaik, Mohammed Nabeel, Mohammed Ashraf,

Yogesh S. Chauhan, Jörg Henkel, Ozgur Sinanoglu, and Hussam Amrouch

Power Side-Channel Attacks in Negative Capacitance Transistor (NCFET)

IEEE Micro, DOI 10.1109/MM.2020.3005883

Preprint arXiv:2007.03987 (2020)

Abstract: Side-channel attacks have empowered bypassing of cryptographic components in circuits. Power side-channel (PSC) attacks have received particular traction, owing to their non-invasiveness and proven effectiveness. Aside from prior art focused on conventional technologies, this is the first work to investigate the emerging Negative Capacitance Transistor (NCFET) technology in the context of PSC attacks. We implement a CAD flow for PSC evaluation at design-time. It leverages industry-standard design tools, while also employing the widely-accepted correlation power analysis (CPA) attack. Using standard-cell libraries based on the 7nm FinFET technology for NCFET and its counterpart CMOS setup, our evaluation reveals that NCFET-based circuits are more resilient to the classical CPA attack, due to the considerable effect of negative capacitance on the switching power. We also demonstrate that the thicker the ferroelectric layer, the higher the resiliency of the NCFET-based circuit, which opens new doors for optimization and trade-offs.

Fig: (a) NCFET structure,with ferroelectric layer integrated inside the transistor’s gate stack;

(b) Equivalent caps series, where the internal voltage exhibits a greater voltage (V_int  > V_G)

Acknowledgments: This work was supported in part by the Center for Cyber Security (CCS) at New York University Abu Dhabi (NYUAD). The work of Satwik Patnaik was supported by the Global Ph.D. Fellowship at NYU/NYUAD. Besides, parts of this work were carried out on the HPC facility at NYUAD.

[paper] Principles and Trends in Quantum Nano-Electronics and Nano-Magnetics for Beyond-CMOS Computing

Ian A. Young and Dmitri E. Nikonov 

Components Research, Technology & Manufacturing Group

Intel Corp., Hillsboro, Oregon, USA

ESSDERC/ESSCIRC Leuven Sept.12-14, 2017

Abstract: An analysis of research in quantum nanoelectronics and nanomagnetics for beyond CMOS devices is presented. Some device proposals and demonstrations are reviewed. Based on that, trends in this field are identified. Principles for development of competitive computing technologies are formulated. Results of beyond-CMOS circuit benchmarking are reviewed.

TABLE I: Voltage Limitations For Computation Variables

Principle 1: Beyond-CMOS circuits require CMOS as an integral part. They will work alongside and augment CMOS computing blocks.

Principle 2: Some devices utilize collective states; this confers advantages of non-volatility or more energy efficient operation.

Principle 3: The choice for an optimal beyond-CMOS device will be determined by compatibility with an efficient and effective interconnect.

Principle 4: Low voltage devices – most direct way to low energy operation.

Principle 5: Start benchmarking with bottom up modeling of devices, build up from simple to more complicated circuits.

Principle 6: Majority gates (if easily implemented in a certain technology) enable more efficient circuits, especially for more complex computation functions.

Principle 7: Use electrical interconnects for longer propagation spans.

Principle 8: To convince the wider community, a non- volatile computing paradigm needs to be general enough to prove that it is valid for more than one architecture; while it needs to be specific enough to dispel claims that an essential aspect is missed.

Principle 9: Neuromorphic computing can be done more efficiently with beyond-CMOS circuits.

Conclusions: In summary, we have presented our view on the recent trends in quantum nanoelectronics and nanomagnetics for beyond CMOS devices, and outlined a few principles to make them realize practical computing technologies. We can pose a question for ourselves: What are the most promising directions of research? Where to double down on the effort? Among many equally important thrusts, our subjective preference is for magnetoelectric switching and neuromorphic beyond-CMOS circuits.