Jun 10, 2020

[paper] Nanowire gate-all-around MOSFETs modeling

Cheng, He, Tiefeng Liu, Chao Zhang, Zhijia Yang, Zhifeng Liu, Kazuo Nakazato
and Zhipeng Zhang
Nanowire gate-all-around MOSFETs modeling:
ballistic transport incorporating the source-to-drain tunneling
Japanese Journal of Applied Physics (2020)
Accepted Manuscript online 5 June 2020
DOI: 10.35848/1347-4065/ab99db

Abstract: Incorporating the source-to-drain tunneling current valid in all operating regions, an analytical compact model is proposed for cylindrical ballistic GAA-nMOSFETs with ultra-short Silicon channel. From taking the DIBL effect into consideration, the potential distribution within the device channel has been modeled based upon a 2-D analysis in our previous work. In this study, by introducing a parabolic function when modeling the potential profile in the channel direction, we found out that the source-to-drain tunneling effect in the subthreshold region could be evaluated analytically by applying WKB approximation. Then, it is practical to estimate the drain current for all operating regions analytically with this compact model considering both the source-to-drain tunneling and thermionic transport. The resulting analytic compact model is tested against NEGF simulation using SILVACO, and good accuracy is demonstrated. Finally, we perform an NMOS inverter circuit simulation using HSPICE, introducing our model to it as a Verilog-A script.

Fig: Rough sketch of the potential energy profile along the channel and illustration of mechanisms governing the carrier transport in ballistic tunneling and thermionic modes.
(a) Representation of energy levels distribution along the z-direction at the channel center (r = 0).
(b) Schematics of confinement potential energy distribution along r-component at the barrier top (z = zMAX) in the cross section. The elementary charge stands for letter e. 

Acknowledgment: The authors would like to thank Prof. S. Uno for his support to this work. This work has been supported by the science and technology program of Liaoning, the major industrial projects (Grant No. 2019JH1/1010022


Jun 9, 2020

Virtual Education Events at ESSDERC/ESSCIRC 2020


Given this uncertain situation, the organizing committee of ESSDERC/ESSCIRC 2020 in Grenoble and its Steering Committee, have decided to propose a new format for coming conference, which will include a NEW and Virtual Education Event series being developed for September 14th 2020 consisting of 13 educational sessions (workshops and tutorial) comprising invited presentations by leading academic and industrial experts and technologists. All related technical program details are also available online: https://www.esscirc-essderc2020.org/educationals

1. TUTORIAL | Quantum Computing: Myth or Reality?
Chairs: M. Vinet (CEA) and Farhana Sheikh (Intel)
Full content duration ~6h
2. WORKSHOP | Emerging Solutions for Imaging Devices, Circuits and Systems
Chairs: Matteo Perenzoni (FBK) and Albert Theuwissen (Harvest Imaging)
Full content duration ~6h
3. WORKSHOP | Non-Volatile Memories: Opportunities and Challenges from Devices to Systems
Chairs: Gabriel Molas (CEA) and Mahmut Sinangil (TSMC)
Full content duration ~6h
4. WORKSHOP | New 5G integration solutions, and related technologies (from materials to system)
Chairs: Nadine Collaert (imec) and Stefan G. Andersson (Ericsson)
Full content duration ~6h
5. WORKSHOP | Advances in device technologies for automotive industry (power devices, SiC, GaN)
Chairs: Ionut Radu (Soitec) and Stefaan Decoutere (IMEC)
Full content duration ~6h
6. WORKSHOP | Embedded monitoring and compensation design for energy or safety constrained applications
Chairs: Sylvain Clerc (ST) and Keith Bowman (Qualcomm)
Full content duration ~4h
7. WORKSHOP | Edge AI and In-Memory-Computing for energy efficient AIoT solutions​
Chairs:  Andreas Burg (EPFL) and Marian Verhelst (KUL)
Full content duration ~6h
8. WORKSHOP | Ab-initio simulations supporting new materials & process developments
Chairs: Denis Rideau (ST) and Philippe Blaise (Silvaco)
Full content duration ~3h
9. WORKSHOP | RISC-V cooking session
Chairs: Bora Nikolic (BWRC)
Full content duration ~3h
10. DISSEMINATION WORKSHOP |  Toward sustainable IOT from rare materials to big data
Chairs:  Thierry Baron (CEA, LTM/UGA) and Audrey Dieudonné (UGA)
Full content duration ~3h
11. DISSEMINATION WORKSHOP | High Density 3D CMOS Mixed-Signal Opportunities
Chair: Philipp Häfliger (UiO)
Full content duration ~3h
12. MOS-AK WORKSHOP | Compact/SPICE Modeling and its Verilog-A Standardization
Chair: Wladek Grabinski (MOS-AK) and Daniel Tomaszewski (ITE Warsaw)
Full content duration ~6h
13. IPCEI on Microelectronics: Innovative Technologies for Shaping the Future
Chairs: Dominique Thomas (ST), Klaus Pressel (Infineon), Rainer Pforr (Zeiss)
Full content duration ~6h

Jun 8, 2020

2020 IEEE ED Poland Chapter MQ

Date
2020-06-26
Location
Virtual
Region
IEEE Region 8 (Europe, Middle East and Africa)
Contact
Krzysztof Górecki – k.gorecki@we.am.gdynia.pl
Description
Distinguished Lecturer
Arokia Nathan - Oxide Electronics Univ. Cambridge (UK)
Mina Rais-Zadeh - MEMS development at JPL (US)
Benjamin Iniguez - Universitat Rovira i Virgili, Tarragona (SP)
Teodor Gotszalk - TU Wrocław (PL)
Mike Schwarz - MEMS Design & Simulation, Bosch (D)

REGISTER at the MQ site
https://eds.ieee.org/education/distinguished-lecturer-mini-colloquia-program/upcoming-dl-and-mq-events?eid=731&m=10e18da593444dc0cb20a2f377717f95

[paper] NESS

Nano-electronic Simulation Software (NESS): 
a flexible nano-device simulation platform
Salim Berrada, Hamilton Carrillo-Nunez, Jaehyun Lee, Cristina Medina-Bailon, Tapas Dutta, Oves Badami, Fikru Adamu-Lema, Vasanthan Thirunavukkarasu, Vihar Georgiev and Asen Asenov 
Journal of Computational Electronics (2020)
DOI: 10.1007/s10825-020-01519-0

Abstract: The aim of this paper is to present a flexible and open-source multi-scale simulation software which has been developed by the Device Modelling Group at the University of Glasgow to study the charge transport in contemporary ultra-scaled Nano-CMOS devices. The name of this new simulation environment is Nano-electronic Simulation Software (NESS). Overall NESS is designed to be flexible, easy to use and extendable. Its main two modules are the structure generator and the numerical solvers module. The structure generator creates the geometry of the devices, defines the materials in each region of the simulation domain and includes eventually sources of statistical variability. The charge transport models and corresponding equations are implemented within the numerical solvers module and solved self-consistently with Poisson equation. Currently, NESS contains a drift–diffusion, Kubo–Greenwood, and non-equilibrium Green’s function (NEGF) solvers. The NEGF solver is the most important transport solver in the current version of NESS. Therefore, this paper is primarily focused on the description of the NEGF methodology and theory. It also provides comparison with the rest of the transport solvers implemented in NESS. The NEGF module in NESS can solve transport problems in the ballistic limit or including electron–phonon scattering. It also contains the Flietner model to compute the band-to-band tunneling current in heterostructures with a direct band gap. Both the structure generator and solvers are linked in NESS to supporting modules such as effective mass extractor and materials database. Simulation results are outputted in text or vtk format in order to be easily visualized and analyzed using 2D and 3D plots. The ultimate goal is for NESS to become open-source, flexible and easy to use TCAD simulation environment which can be used by researchers in both academia and industry and will facilitate collaborative software development.
FIG: Flowchart of NESS detailing its modular structure

NESS will be released in the summer of 2020 as an open-source software which makes it very interesting for both academia and industry in helping to address the challenges subsequent to the further down-scaling of CMOS components.

Acknowledgements: This work was supported by the European Union’s Horizon 2020 research and innovation programme under Grant Agreement No. 688101 SUPERAID7. Also, this project has received funding from EPSRC UKRI under Grant Agreements No. EP/S001131/1 (QSEE) and No. EP/P009972/1 (QUANTDEVMOD).

Semi-talk: Low Cost Photonics | Dr. Naresh Chand, Life Fellow of IEEE, Associate Vice President, Chapter Relations of the IEEE Photonics Society https://t.co/mQkIAGoI51 #paper https://t.co/zmPh8QDa3F


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