[paper] Compact Device Models for FinFET and Beyond

D. D. Lu, M. V. Dunga, A. M. Niknejad, C.Bing Hu, F.-X. Liang, W.-C. Hung, J. Lee, C.-H. Hsu
and M.-H. Chiang,

Compact device models for FinFET and beyond

ArXiv, vol. abs/2005.02580, 2020

Abstract - Compact device models play a significant role in connecting device technology and circuit design. BSIM-CMG and BSIM-IMG are industry standard compact models suited for the FinFET and UTBB technologies, respectively. Its surface potential based modeling framework and symmetry preserving properties make them suitable for both analog/RF and digital design. In the era of artificial intelligence / deep learning, compact models further enhanced our ability to explore RRAM and other NVM-based neuromorphic circuits. We have demonstrated simulation of RRAM neuromorphic circuits with Verilog-A based compact model at NCKU. Further abstraction with macromodels is performed to enable larger scale machine learning simulation.

Fig: Simulation of a novel floating - gate synaptic transistor. (a) Device structure with separate negative feedback gate (nfb) for programming and synaptic gate (sg) readout. (b) Equivalent circuit diagram for compact modeling 

Acknowledgements - The authors would like to express sincere gratitude to Chip Implementation Center (CIC), Hsinchu, Taiwan for providing SPICE simulation environment for RRAM simulations.

[PhD] Compact DC Modeling of Tunnel-FETs

Compact DC Modeling of Tunnel-FETs

November 2019

PhD Thesis of Fabian Horst 

Doctor Advisor: Profs. Benjamin Iniguez and Alexander Kloes

Abstract - In the last decade, the tunnel field-effect transistor (TFET) has gained a lot of interest and is handled as a possible successor of the conventional MOSFET technology. The current transport of a TFET is based on the band-to-band (B2B) tunneling mechanism and therefore, the subthreshold slope at room temperature can overcome the limit of 60 mV/dec. In order to describe and analyze the TFET behavior in circuit simulations, this dissertation introduces a compact DC model for double-gate TFETs. The modeling approach considers the B2B tunneling and the parasitic effect of trap-assisted tunneling (TAT) in the ON- and AMBIPOLAR-state of the TFET. It includes a 2D compact potential equation package to de-scribe the band diagram of the TFET. Based on the band diagram, the B2B tunneling and TAT current part are derived separately. In order to do so, firstly a compact expression for the tunneling length is found, which is then used together with a numerical robust Wentzel-Kramers-Brillouin (WKB) approach to calculate the tunneling probability. Afterwards, using Landauer’s tunneling equation, the tunneling generation rate is calculated and approximated to come to a closed-form expression for the current density. Further approximation of the current density by a mathematical function, compact expressions for the resulting B2B tun-neling and TAT current are achieved. The verification of the model is done with the help of TCAD Sentaurus simulation data for various simulation setups. Furthermore, the validity of the model is proven by measurements of fabricated complementary TFETs. In order to demonstrate the numerical stability and continuity as well as the flexibility, simulations of TFET-based logic circuits like a single-stage inverter or an SRAM cell are performed and analyzed. The combination of the DC model with an TFET AC model allows for a transient simulation of an 11-stage ring oscillator. 

Fig: 2D sketch of the n-type DG TFET device geometry, showing the channel thickness t ch , the channel length l ch , the gate oxide thickness tox and the length of the S/D region l sd . Source (S) and drain (D) region are highly p/n-doped with a doping concentration N s/d 

URL: http://hdl.handle.net/10803/668957

IEEE EDS DL Series by the EDS Delhi Chapter

	IEEE Electron Device Society (EDS) Delhi Chapter – India & Department of Electronic Science University of Delhi South Campus, New Delhi, India
Jointly Organizes

EDS Distinguished Lecture

(Live Session under EDS Distinguished Lecturer Program - Virtual Lectures)

Online Live Webinar Lecture Schedule (via Google Meet)

April 30, 2020 at 10:30 am (past event) High-k Dielectric and Interface Engineering for High Performance Si/Ge MOS and FinFETs	Kuei-Shu Chang-Liao Department of Engineering and System Science National Tsing Hua University, Hsinchu, Taiwan
May 01, 2020 at 10:30 am  (past event) Two-dimensional Layered Materials for Nanoelectronics	Yang Chai Associate Professor, Department of Applied Physics The Hong Kong Polytechnic University
May 05, 2020 at 01:30 pm (past event) Introducing two-dimensional layered dielectrics in solid-state micro-electronic devices	Mario Lanza Institute of Functional Nano & Soft Materials, Soochow University, Collaborative Innovation Center of Suzhou Nano Science & Technology, China
May 06, 2020 at 06:30 pm (past event) Field Effect Transistors: From MOSFET to Tunnel-FET	Joao Antonio Martino Professor at University of Sao Paulo, Brazil
May 08,2020 at 06:30 pm IST Junctionless Nanowire Transistors: Electrical Characteristics and Compact Modeling	Marcelo Antonio Pavanello Centro Universitario FEI, Department of Electrical Engineering Av. Humberto de Alencar Castelo Branco, Sao Bernardo do Campo,  Brazil
May 11, 2020 at 01:30 pm IST From CMOS to Neuromorphic Computing - A peek into the future	Maria Merlyne De Souza Department of Electronic and Electrical Engineering The University of Sheffield, United Kingdom
May 12, 2020 at 10:30 am IST Phase change electro-optical devices for space applications	Mina Rais-Zadeh Group Supervisor, Advanced Optical and Electromechanical Microsystems Group, Micro Device Laboratory, NASA JPL, Pasadena, CA
May 15, 2020 at 08:30 pm IST State-of-the-Art Silicon Very Large Scale Integrated Circuits: Industrial Face of Nanotechnology	Michael S. Shur  Electrical, Computer and Systems Engineering and Physics, Applied Physics, and Astronomy Rensselaer Polytechnic Institute
May 16, 2020 at 02:00 pm IST Transparent and Flexible Large Area Electronics	Arokia Nathan  Cambridge Touch Technologies,  University of Cambridge, United Kingdom (UK)
May 20, 2020 at 02:30 pm IST Trends and challenges in Nanoelectronics for the next decade	Elena Gnani  Department of Electrical, Electronic and Information Engineering, University of Bologna, Italy
May 22, 2020 at 07:30 pm IST Accelerating commercialization of SiC power electronics	Victor Veliadis Executive Director and CTO, Power America Professor of Electrical and Computer Engineering,  North Carolina State University
May 27, 2020 at 07:30 pm IST Advanced III-N Devices for 5G and Beyond	Patrick Fay Department of Electrical Engineering,  University of Notre Dame

More talks will be added so if you wish to attend any of these then then kindly register on:

https://docs.google.com/forms/d/e/1FAIpQLSddt6Dq53G1aK4kk_ulyUiqc0_m_Be1lXxcXYxdULhANxB09Q/viewform

Coordinated by:

Dr. Manoj Saxena, SMIEEE, FIETE, MNASc (India) EDS BoG Member (2018-2020) & EDS DL Regional Editor for South Asia, IEEE EDS Newsletter Associate Professor, Department of Electronics  Deen Dayal Upadhyaya College, University of Delhi  Dwarka Sector-3, New Delhi, India; Email: msaxena@ieee.org

Professor Mridula Gupta, SMIEEE, FIETE Chairperson-IEEE EDS Delhi Chapter Head, Department of Electronic Science University of Delhi South Campus New Delhi 110021, India Email: mridula@south.du.ac.in

[paper] A Compact Model for SiC Schottky Barrier Diodes Based on the Fundamental Current Mechanisms

J. R. Nicholls and S. Dimitrijev

Queensland Micro- and Nanotechnology Centre

School of Engineering and Built Environment

Griffith University, Brisbane, QLD 4111, Australia

A Compact Model for SiC Schottky Barrier Diodes Based on the Fundamental Current Mechanisms

IEEE Journal of the Electron Devices Society

doi: 10.1109/JEDS.2020.2991121.

Abstract - We develop a complete compact model to describe the forward current, reverse current, and capacitance of SiC Schottky barrier diodes. The model is based on the fundamental current mechanisms of thermionic emission and tunneling, and is usable over a large range of voltages, temperatures, and for a large range of device parameters. We also demonstrate good agreement with measured data. Furthermore, the development of this model outlines a methodology for transforming a tunneling equation into a compact form without numerical integration-this methodology can potentially be applied to other device structures.

Fig: (a) Structure of a Schottky barrier diode. (b) Equivalent circuit of a Schottky barrier diode, consisting of two current sources (for the forward and reverse bias currents), a shunt capacitance and a series resistance

Acknowledgement - This work was performed at the Queensland Microtechnology Facility (Griffith University), part of the Queensland node of the Australian National Fabrication Facility (ANFF), a company established under the National Collaboration Research Infrastructure Strategy to provide nanofabrication and microfabrication facilities to Australia’s researchers. 

URL: https://ieeexplore.ieee.org/stamp/stamp.jsp?tp=&arnumber=9081977&isnumber=6423298

[paper] Two Transistors Voltage-Measurement-Based Test Structure for Fast MOSFET Device Mismatch Characterization

J. P. M. Brito and S. Bampi

Two Transistors Voltage-Measurement-Based Test Structure 

for Fast MOSFET Device Mismatch Characterization

IEEE Transactions on Semiconductor Manufacturing

doi: 10.1109/TSM.2020.2988095

Abstract - This work presents a test structure targeted to measure MOSFET mismatches with a fast method. It relies on two single-spot voltage measurements in order to extract VTH and β/β separately. The new methodology gives a theoretical increase in the measurement speed of 30x (23.17x in practice). The coefficient of determination (R2) of the linear regression analysis is used to compare standalone transistor measurements against the new proposed methodology. The correlation in the data demonstrates values not less than 0.94 (R2≥ 0.94). The test structure can reproduce parameter correlations, and it is capable of extracting MOSFET mismatch design parameters, such as Pelgrom’s AVTH, with an error of 2% and Aβ, with a negligible error. The experimental data presented herein are taken from measurements in prototypes fabricated in a 65nm CMOS bulk process. The whole circuit is composed of 16 2D addressable DUT device matrices, each having 256 same-size closely-placed MOSFET devices, totaling 4,096 MOS devices used in single-type (NMOS) transistor array. 

URL: https://ieeexplore.ieee.org/stamp/stamp.jsp?tp=&arnumber=9068274&isnumber=5159394