[paper] Open Source EZ130 8T standard cell library

Oscar Castaneda, Lavinia Recchioni, Tobias Senti, Flurin Cahenzli, Marco Ferroni, Thorben Heekenjann, Robert Kenter, Stefan Odermatt, Daniel Richner, Gabriel Altendorfer, Davide Cannone, Miguel Correa, Ivan Herger, Lars Kroger, Nicolas Nanzer, Darja Nonaca, Christopher Reinwardt, Lukas Winklhofer, Enrico Zelioli, Yiheng Zhang, Yingxue Zhang, Domenic Keller, Seyed Hadi Mirfarshbafan, Zerun Jiang, Beat Muheim, Arianna Rubino, Jeremy Guichemerre, Frank K. Gurkaynak, and Christoph Studer

An Open-Source Standard-Cell Library for IHP 130 nm Developed by Students

arXiv:2609.29965v1 [cs.AR] 24 Sep 2026

1. Department of Information Technology and Electrical Engineering, ETH Zurich, Switzerland

* The open-source EZ130 8T standard-cell library is available at https://ez.ethz.ch

Abstract: Standard-cell libraries form the critical interface between transistor-level circuit design and automated digital design flows, yet their design and characterization are rarely covered in depth in digital VLSI courses. This paper presents VLSI 5, a graduate-level course at ETH Zurich in which students design, lay out, characterize, and integrate their own standard cells using IHP’s open-source 130 nm SG13G2 process design kit. In the first course offering, 19 students developed EZ130 8T, an open-source eight-track standard-cell library comprising 220 cells. We evaluate successive library versions using eight synthesis benchmarks, across which EZ130 8T achieves significant area reduction compared to the SG13G2 library at competitive timing. For a postlayout 8×8 matrix-vector multiplier, EZ130 8T reduces cell area by 35% and energy by 39% while maintaining virtually the same clock period. The library has already been adopted in other ETH Zurich VLSI courses, enabling the creation of chips entirely designed by students down to the transistor level.

FIG: a.) ETH Zurich course series on digital VLSI design. By teaching students to create a standard-cell library, the new VLSI 5 course closes the gap between transistor-level and HDL-level IC design;
b.) and c.) Layout of two example standard cells from the EZ130 8T library.

Aknowlegements: This work has received funding from the Swiss State Secretariat for Education, Research, and Innovation (SERI) under the SwissChips initiative. The authors thank Cadence for their support by providing licenses to design and characterize the EZ library. The authors also thank H. Pretl, T. Benz, and P. Sauter for their feedback on preliminary versions of the EZ library.