IEEE EDS Distinguished Lecturer by ED Poland Chapter

IEEE EDS Distinguished Lecturer by ED Poland Chapter

Krzysztof Górecki and Daniel Tomaszewski

EDS Distinguished Lecturer, Professor Mansun Chan (UST, Hong Kong) gave a talk titled “Simulation and Modeling of Dynamic Systems with Time Varying Device Characteristic” on May 21, 2019, at Łukasiewicz Research Network—Institute of Electron Technology (Łukasiewicz ITE), Warsaw, Poland. Approximately 15 persons from ITE and from abroad, traveled to Warsaw for the ESSDERC paper selection meeting and to attend the lecture.

The abstract of the Distinguished Lecture: The existing circuit simulation methodologies are based on time-invariant device models, electrical characteristics and parameters of which do not change over time. However, more recently, many new applications such as neuromorphic computing or artificial neural-network circuits require the use of devices with history dependent behavior. Due to such a behavior different from traditional transistors, which are the focus for the compact modeling community, a new approach to monitor the time dependent characteristics of these devices is necessary. In addition, a new simulation methodology is also required to predict the behavior of such system efficiently. In the presentation, a new approach to simulate dynamic systems was introduced. The proposed approach combined with the modification of simulation flow and compact model construction was introduced. The approach is very general and can be used to cover a wide class of devices with dynamic behavior such as memory function or device performance degradation during a prolonged operation.

A Mini-Colloquium was organized by the ED Poland Chapter in cooperation with: Gdynia Maritime University, Gdynia, Poland, Łukasiewicz Research Network—Instytut Technologii Elektronowej (Łukasiewicz-ITE), Warsaw, Poland, and a Department of Microelectronics and Computer Science, Lodz University of Technology, Lodz, Poland. Approximately 20 persons attended the full-day event. Nine interesting talks were presented by internationally recognized experts in the area of nanoelectronics, including three EDS Distinguished Lecturers (DLs).

Prof. Shinichi Takagi (The University of Tokyo) presented a talk “Tunneling FET technology for ultra-low power logic applications” addressing critical issues, technical challenges and viable technologies of TFETs using a variety of semiconductors such as Si, Ge and oxide semiconductors. Device engineering indispensable in improving the performance of TFETs were summarized with emphasis on the source junction formation technology and the optimal material design. The electrical characteristics of TFETs using Si and Ge homo junctions, Ge/strained SOI hetero-junctions and ZnO/(Si, Ge) hetero-junctions were presented as the viable examples.

Prof. Andrzej Strójwąs (PDF Solutions, and Carnegie Mellon University) had a talk “New Product Introduction Challenges in the Bleeding Edge Technology Nodes,” presenting a comprehensive methodology and a full suite of process-design design interaction characterization techniques to enable cost-effective introduction of new products in the 7 nm and below technologies.

Dr. Arkadiusz Malinowski (GlobalFoundries) gave a talk “Will FinFET era last only for 10 years? FinFET scaling challenges for next CMOS technology nodes,” in which challenges related to FinFET metrology/inspection, lithography/overlay, integration/variability, cycle time and cost were addressed.

Dr. Rajiv V. Joshi (DL, IBM Research Division Yorktown Heights) presented a lecture “Variability aware design in nm era.” He highlighted predictive analytical technique based on statistical analysis methodology targeting both memory and custom logic design applications is highlighted. Design case studies both in planar and non-planar technologies were discussed. Finally, the speaker discussed an efficient statistical methodology based on simulation and modeling to evaluate and minimize the aging of memory chips.

Prof. Henryk M. Przewłocki (DL, Łukasiewicz Research Network—ITE Warsaw) presented a talk “Expanding the horizon of photoelectric investigations of the MIS system properties,” in which he discussed an extended theory of the photocurrent vs. gate voltage characteristics, at different wavelengths of light illuminating the structure under test, with diffusion currents taken into account. The theory is in agreement with the relevant experimental characteristics. This opens the possibilities of developing new measurement methods of the MIS system crucial parameters.

Prof. Marcelo Pavanello (DL, Centro Universitario FEI) presented a talk “Performance and modeling of Nanowire-based MOSFETs.” He discussed differences between double-gate, triple-gate and nanowire-based MOSFETs and their characteristics. Also junctionless nanowire transistors (JNTs) were introduced as one of the interesting alternatives for downscaling because of their relative process simplicity compared with inversion-mode nanowires. Different aspects of modeling of the JNT steady-state and dynamic operation was interestingly presented.

Dr. Farzan Jazaeri (EPFL) presented a talk “Cryogenic Electronics and Quantum Computing Architecture.” He made an interesting review of topics of a quantum computation that holds the promise to solve problems that are intractable even for the most powerful supercomputers. Quantum computers process the information stored in quantum bits (qubits). The information in the qubits is fragile, so the qubits must be typically cooled to cryogenic temperature. Spin qubits in silicon were reported that have already been proposed and experimentally demonstrated in academic research laboratories.

Prof. Mike Brinson (London Metropolitan University) presented a talk “Equation-Defined template and synthesis driven compact modelling of semiconductor devices.” He reported current research that links Equation-Defined Device modelling with Verilog-A modules, driven by code templates and synthesis, which in turn result in an improved interactive modelling techniques. Throughout the talk a series of compact device models were introduced to demonstrate the fundamentals and application of the new approach to compact device modelling.

Dr. Władek Grabiński (DL, MOS-AK and GMC) presented a talk “FOSS tools for support of IC modeling and design with special emphasis on Verilog-A standardization.” He discussed selected FOSS CAD tools along complete technology/design tool chain from nanoscaled technology processes. The talk was illustrated by application examples of the FOSS TCAD tools, like Cogenda TCAD and DEVSIM. Compact modeling was related to the parameter extraction and standardization of the experimental and measurement data exchange formats. Finally, present FOSS CAD simulation and design tools: ngspice, Qucs, GnuCap, Xyce were presented.

~ Marcin Janicki, Editor