[paper] EKV-gm/ID Design Procedure

Marcello De Matteis

MATLAB-Assisted EKV-gm/ID Design Procedure for Two-Stage Miller-Compensated CMOS OTAs Starting from Closed-Loop Specifications

Journal of Low Power Electronics and Applications 16, no. 4: 53

DOI: 10.3390/jlpea16040053

Department of Physics, University of Milano Bicocca, Piazza della Scienza 3, 20126 Milano, Italy

Abstract: This paper presents a MATLAB-assisted EKV–gm/ID methodology for the systematic synthesis of fully differential two-stage Miller-compensated CMOS OTAs. A sensitivity-based analysis maps the required closed-loop gain, bandwidth, and noise into OTA-level targets. An EKV-inspired analytical model, independently calibrated for nMOS and pMOS devices, provides continuous ID/W, gm/W and gm/ID characteristics with errors below 5% in the design region. Noise-driven sizing explicitly accounts for the different carrier mobilities of the pMOS differential pair and nMOS active load. Transistor parasitic capacitances are estimated from bias-dependent Cgg–VGS characteristics, thereby capturing the reduced gate capacitance of devices operating in moderate or weak inversion. The framework automatically generates transistor dimensions, bias conditions, and Miller-compensation components. These parameters are transferred directly from MATLAB to CADENCE without simulator-assisted resizing or optimization, except for width quantization into 5 μm/300 nm fingers. In 0.18 μm CMOS implementation, MATLAB and nominal commercial CAD simulations predict, respectively, 61.80 and 59.27 dB DC gain, 430.78 and 431.52 MHz unity-gain bandwidth, 69.24° and 68.81° phase margin, 5.0 and 5.3 nV/√Hz input-referred noise at 100 MHz, and 1.426 and 1.314 mW core power. Robustness is assessed over 45 process-voltage-temperature corners, where the nominal solution remains close to the center of the evaluated performance distributions. The results confirm accurate nominal prediction and stable transistor-level behavior across PVT conditions and demonstrate that the proposed methodology accurately designs the OTA operating point, small-signal dynamics, and noise behavior, enabling transistor-level sizing directly from system-level specifications without iterative simulator-assisted optimization.

FIG.1: From Closed-Loop Specifications to a PVT-Verified OTA; MATLAB-Assisted EKV gm-ID Synthesis without Iterative Transistor Level Optimization

FIG.2: Design flow-chart for the two-stage Miller-compensated OTA.

[paper] Design techniques for low-voltage analog integrated circuits

Matej Rakus, Viera Stopjakova, Daniel Arbet

Institute of Electronics and Photonics, Faculty of Electrical Engineering

and Information Technology Slovak University of Technology in Bratislava, Slovakia,

Journal of ELECTRICAL ENGINEERING, Vol.68 (2017), No.4, 245–255

DOI: 10.1515/jee-2017–0036

ABSTRACT: In this paper, a review and analysis of different design techniques for (ultra) low-voltage integrated circuits (IC) are performed. This analysis shows that the most suitable design methods for low-voltage analog IC design in a standard CMOS process include techniques using bulk-driven MOS transistors, dynamic threshold MOS transistors and MOS transistors operating in weak or moderate inversion regions. The main advantage of such techniques is that there is no need for any modification of standard CMOS structure or process. Basic circuit building blocks like differential amplifiers or current mirrors designed using these approaches are able to operate with the power supply voltage of 600 mV (or even lower), which is the key feature towards integrated systems for modern portable applications.

Fig: Parameter gm/ID versus the normalized drain current. MOS transistor operates in weak inversion (WI) for i_c < 0.1. Strong inversion (SI) is for i_c < 10. Everything in between belongs to the moderate inversion (MI) with center in i_c = 1