[rsvNumerics] hands-on transistor sizing for analog ICs

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rsvNumerics provides concepts, guidance and software tools for sizing transistors in integrated circuits with an easy-to-learn methodology. Whether you are a novice or an expert, you can benefit from our methodology and dimension your devices in no time, serving as a near-perfect starting point for your verification. Moreover, our methodology is not limited to a few predefined circuit topologies; it works for literally any circuit in any application.

Constant-𝑔𝑚 Biasing Circuit Example 

rsvNumerics in Circuit Design General, SizingTool

The schematic of the constant-𝑔𝑚 bias circuit is shown above. It consists of two cross-coupled current mirrors, where one of the source contacts, e.g. of an NMOS transistor, is degenerated by a source resistor. This results in a unique operating point of the circuit other than zero current, which defines the pass current in the two branches.

The corresponding settings of SizingTool 3 for transistor 𝑁𝑀0 and for transistor 𝑁𝑀1 are given in Fig above. Once the drain currents for a constant-𝑔𝑚 biasing block are known, we can use the information when designing any other transistor with derived source current. However, there its drain current has to be readjusted each time the process corner is changed to reflect for constant-𝑔𝑚 biasing, which is tedious, and is addressed by the current weighing option.

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[paper] Gradient Minimization in Layout Patterns for Analog Circuits

Isaac Bruce, Michael Sekyere, Ruohan Yang, Saeid Karimpour, Colin C. McAndrew, Degang Chen

Gradient Minimization in Layout Patterns for Analog Circuits

Circuits, Systems, and Signal Processing. 1-22.

DOI: 10.1007/s00034-025-03158-x

1 Department of Electrical and Computer Engineering, Iowa State University, Ames, IA, USA

 

Abstract: In this paper, we present an algorithm to generate the layout of a pair of devices A and B for a given matching ratio r and total unit cell count N that minimizes the mismatch due to systematic gradient effects. The algorithm relies on simple reflections and rotations of an initial optimized pattern across 4 quadrants. The approach cancels all odd-order systematic gradients and minimizes 2nd order systematic gradients. The method can easily be extended to cancel higher-order even gradient effects. The validity of the proposed algorithm is demonstrated via numerical simulations. Additionally, an electrothermal simulation of a set of layouts is run to further validate the proposed layout generation scheme.

FIG: Layout of circuit design with heat sources and current sources 

for the optimal transistor array pattern.

[mos-ak] 一生一芯 2025 Summer Launch Conference

 One Student, One Chip

2025 Summer Launch Conference

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🗓 Conference Details

• Date & Time: July 21st (Monday), 14:30
• Location: Room 104, Mingde Campus, Shenzhen University, Nanshan District, Shenzhen, Guangdong Province
• Participation: Online registration open until July 19th, 23:59
• Live Stream: Bilibili Live Broadcast Link

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🎓 About the Project

The "One Student One Chip" (一生一芯, ysyx.org) program is an open-source, free, and public training platform aimed at developing full-stack engineers proficient in both hardware and software. It's designed for lifelong learners of all ages—from primary school to university—without limitations. Students are guided in designing and implementing a RISC-V CPU, using:

• Chisel (hardware description language)
• FPGA tools
• DK development environment

They explore concepts spanning:

• Digital logic
• RTL design
• Computer architecture
• Operating systems
• Compilers

Since its 2019 launch, the program has involved over 12,000 students, with backing from top universities including Tsinghua, Peking, and Fudan.

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🌟 Key Highlights for 2025

1. New teaching materials with a hierarchical learning model (EDCBA) to enhance learning efficiency
2. Post-course chip design program with ECOS Studio tools and open-source test platforms
3. Launch of MOLI Learning Platform, offering curated courses from universities like MIT, Tsinghua, and Peking University

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🏫 Supporting Institutions

• Tsinghua University
• Peking University
• Fudan University
• Zhejiang University
• Shanghai Jiao Tong University
• University of Science and Technology of China
• Harbin Institute of Technology
• National University of Defense Technology

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[mos-ak] [Media Note] MOS-AK Workshop, London, July 11, 2025

MOS-AK Workshop 2025 Held at London Metropolitan University [MOS-AK Media Note]

The MOS-AK Compact Modelling Workshop was successfully hosted on July 11, 2025, at London Metropolitan University, bringing together a diverse group of researchers, engineers, and industry professionals to explore recent advances in compact modelling, semiconductor technologies, and circuit simulation. This in-person event marked a valuable opportunity for participants to reconnect face-to-face, exchange ideas, and foster collaboration across institutions and disciplines.

The workshop featured a distinguished panel of presenters from academia, research institutions, and industry. These experts delivered high-quality technical talks covering a broad range of cutting-edge topics in compact device modelling, circuit design, and emerging applications. The presentations covered innovative research and development in the following areas:

• Open PDK Progress: "IHP-Open-PDK Review: Present Status and Future Directions" Dr. Krzysztof Herman -  IHP Leibniz Institute for High Performance Microelectronics

• Open PDK Progress: "The Application of FOSS Tools in the Design of IHP Open-Access 130nm BiCMOS RF Integrated Circuits" Prof. Mike Brinson -  London Metropolitan University

• Open PDK Progress: "Presentation and Evaluation of the 1st IHP Open Source Analog Certificate Course" Phillip Ferreira Baade-Pedersen -  IHP Leibniz Institute for High Performance Microelectronics

• Biomedical Sensing: "Non-invasive Biomedical Sensor for Dehydration Monitoring" Prof. Bal Virdee and Innocent Lubangakene London Metropolitan University (UK)

• Quantum Modelling: "Compact Quantum Dot Models for Analog Microwave Co-Simulation"
  Lorenzo Peri -  Quantum Motion and University of Cambridge

• Cryogenic Electronics: "Deep-Cryogenic Device Characterisation in a CMOS Foundry Process"
  Grayson Noah -  Quantum Motion

• Compact Modelling: "Developments of Compact Models for Source-Gated Devices"
  Dr. Patryk Golec -  École Polytechnique, Paris

• Display and Bio Circuits: "Area- and Energy-Efficient Current-Mode Pixel Circuits for High-Performance Display and Life Science Applications"
  Dr. Eva Bestelink -  University of Surrey

• Novel Transistor Behaviour: "Opportunities for Modelling Off-State Behaviour in Polysilicon Contact-Controlled Transistors"
  Prof. Radu A. Sporea -  University of Surrey

Each session stimulated thoughtful discussion and knowledge sharing among attendees, reinforcing the relevance of compact modelling in enabling innovation across semiconductor technologies.

The event was organized by London Metropolitan University with the support of the Institution of Engineering and Technology (IET) and the IEEE Electron Devices Society, and was generously sponsored by the IHP Leibniz Institute for High Performance Microelectronics.

A total of 35 delegates attended the workshop, representing a mix of academia, research labs, and industry. The workshop concluded with a networking drinks reception, providing attendees a relaxed environment to engage in informal discussions, build professional connections, and explore collaborative opportunities.

-- Prof. Bal Virdee, Prof. Mike Brinson and W.Grabinski for Extended MOS-AK Committee

WG150725

[mos-ak] [Final Program] 22nd MOS-AK/ESSERC Workshop in Munich (D) Sept. 8, 2025

Arbeitskreis Modellierung von Systemen und Parameterextraktion

Modeling of Systems and Parameter Extraction Working Group

MOS-AK/ESSERC Workshop in Munich

September 8, 2025

Scheduled consecutive 22nd MOS-AK/ESSERC SPICE/Compact Modeling T2 Workshop organized in Munich, aims to strengthen a network and discussion forum among experts in the field, enhance open platform for information exchange related to compact/SPICE modeling and Verilog-A standardization, bring people in the compact modeling field together, as well as obtain feedback from technology developers, circuit designers, and FOSS CAD/EDA tool developers and vendors. The content will be beneficial for anyone who needs to learn what is really behind the FOSS CAD/EDA IC simulation in modern device models in OpenPDKs. The MOS-AK workshop program is available online: 

<https://www.mos-ak.org/munich_2025/>

It will be followed by ESSERC T2 Tutorial "Design and Simulation of Analog/RF Integrated Circuits with Open-Source CAD Tools and Process Design Kits". T2 tutorial explores how FOSS CAD/EDA tools and OpenPDKs empower IC designers. T2 also introduces ACM2, a compact, physics-based MOSFET model, with hands-on guidance on design parameter extraction for analog/RF circuit applications using the IHP OpenPDK 130nm BiCMOS process.

Online Registration is open (Early: until Friday July 18, 2025 (23:59 CEST))

any related enquiries can be sent to registration@mos-ak.org

-- W.Grabinski on the behalf of International MOS-AK TPC Committee

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Enabling Compact Modeling R&D Exchange

www.mos-ak.org

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WG140725

[mos-ak] [C4P] Austrochip 2025

Call for Papers – Austrochip 2025

Submission Deadline: July 24, 2025

We, JKU, Local Organizer and Host, are excited to invite submissions for Austrochip 2025 – The 33rd Austrian Workshop on Microelectronics, happening on September 24-25, 2025, in Linz, Austria. This workshop is a key platform for sharing advancements in microelectronics, connecting researchers, and fostering collaboration. If you're working on innovative designs, methodologies, or applications, we'd love to see your work!

For submission details and guidelines, visit: https://iic.jku.at/austrochip/pages/call-for-papers.html

Join us for an exciting workshop and conference on the future of microelectronics!

[mos-ak] [OpenPDK] IHP Analog Academy

IHP Analog Academy

https://lnkd.in/eQnNX4ug

We, IHP Analog Academy, are excited to present this deep dive into analog, RF, and mixed-signal IC design, powered by open-source FOSS CAD/EDA tools and the IHP Open PDK.

This hands-on course is designed for engineers, researchers, and students eager to gain practical experience with the SG13G2 process at the 130nm technology node. Originally hosted on-site at IHP in Frankfurt (Oder), participants spent five intensive days exploring everything from fundamental analog simulation to advanced RF, 3D EM modeling, and mixed-signal integration. And now we're excited to release it to the open-source community!

The course covers:

- Bandgap reference design and simulation using the gm/Id methodology

- RF design of a 50 GHz Medium Power Amplifier with EM simulation

- Mixed-signal integration and verification of an 8-bit SAR ADC

Each module emphasizes a real-world design flow using tools like:

ngspice, Xyce, KLayout, OpenEMS, QUCS, and Python for data analysis.

Over time, we will expand the repository with:

- More modules

- Updated toolchain support

- Improvements to existing flows

Explore the IHP Open PDK:

- Open PDK GitHub Repository https://github.com/IHP-GmbH/IHP-Open-PDK 

- Interactive Help via ChatGPT https://chat.openai.com

Note: This is not an introductory IC design course. A basic understanding of electronics and microelectronics is assumed. We're proud to contribute this initiative to the community to help lower the barrier to IC design using open-source tools. We encourage contributions via GitHub Issues or Pull Requests! Your feedback and contributions, are welcome!

Lead Author: Phillip Ferreira Baade-Pedersen

Co-Author: Christian Wittke

The Development of this course is funded by the public German project FMD-QNC (16ME083) from BMFTR (Federal Ministry of Research, Technology and Space / Bundesministerium für Forschung, Technologie und Raumfahrt): https://www.elektronikforschung.de/projekte/fmd-qnc

#opensource #analog #mixedsignal #rf #design

Compact MOSFET Mechanical Stress Model

Bonev, Nikolay, Dirk Michael Nuernbergk, and Christian Lang

Inclusion of Mechanical Stress Effects in a Compact MOSFET Model

Science and Technology 28, no. 2 (2025): 138-149.

DOI: 10.59277/ROMJIST.2025.2.02

<https://romjist.ro/full-texts/paper797.pdf>

1 Melexis Bulgaria EOOD, Sofia, Bulgaria
2 Melexis GmbH Erfurt, Erfurt, Germany

Abstract: The analog performance of integrated circuits relies on stable parameters of its transistors. Mechanical stress changes the electronic properties of silicon and, therefore, also the device parameters. For circuit design, a good model of these effects is needed for a predictable and reliable function of the circuits. This article extracts the changes of various MOSFET parameters under effect of mechanical stress. A compact description of the stress effects is derived by applying tensors of piezo coefficients. The deviations are included in the physically based compact EKV model. A comparison with measured data shows that the stress effects are modelled correctly within a 10 % error margin.

Fig: Extraction setup for the specific current Is