[Workshop] Open Source PDKs and EDA

 Workshop 1: Open Source PDKs and EDAs, 

Community Experiences toward Democratization of Chip Design

RIHGA Royal Hotel Kyoto, Horikawa Shiokoji, Shimogyo ku, Kyoto 600 8237, Japan.

Date & Time: 5:30pm.-7:15pm on June 11 (Sun), 2023

Since its launch in 2020, the Open MPW shuttle program has received over 500 project submissions spanning 9 shuttles. This workshop will explore various topics related to designers' experiences, including measured results, foundry perspectives, and governmental expectations.

Organizers: 

• Makoto Ikeda (The University of Tokyo)
• Mehdi Saligane (University of Michigan)

Program:

1. Design experience: “The Journey of Two Novice LSI Enthusiasts: Tape-Out of CPU+RAM in Just One Month”, Kazuhide Uchiyama, University of Electro-Communications and Yuki Azuma, University of Tsukuba
2. From Zero to 1000 Open Source Custom Designs in Two Years, Mohamed Kassem, Co-founder and CTO, Efabless
3. The SKY130 Open Source PDK: Building an Open Source Innovation Ecosystem, Steve Kosier, Skywater technology
4. Open Source Chip Design on GF180MCU – A foundry perspective, Karthik Chandrasekaran, Global Foundries
5. Japan Foundries' Perspectives on Silicon design democratization, Shiro Hara, Minimal Fab & AIST
6. Google's perspective on Open source PDKs, Open source EDA tools, and OpenMPW shuttle program, Johan Euphrosine and Tim Ansell, Google
7. The Nanofabrication Accelerator Project, Matthew Daniels, NIST
8. Japanese government perspective on Silicon design democratization, Yohei Ogino, The Ministry of Economy, Trade and Industry METI

VLSI Symposium Workshop1 "Open Source PDKs and EDA" Audience

[book] Tunneling Field Effect Transistors

Tunneling Field Effect Transistors
Design, Modeling and Applications

Edited By T. S. Arun Samuel, Young Suh Song, Shubham Tayal, P. Vimala, Shiromani Balmukund Rahi

ISBN 9781032348766
1st Edition; 316 Pages; 15 Color & 232 B/W Illustrations
June 8, 2023 by CRC Press

Description: This book will give insight into emerging semiconductor devices from their applications in electronic circuits, which form the backbone of electronic equipment. It provides desired exposure to the ever-growing field of low-power electronic devices and their applications in nanoscale devices, memory design, and biosensing applications.

Tunneling Field Effect Transistors: Design, Modeling and Applications brings researchers and engineers from various disciplines of the VLSI domain to together tackle the emerging challenges in the field of nanoelectronics and applications of advanced low-power devices. The book begins by discussing the challenges of conventional CMOS technology from the perspective of low-power applications, and it also reviews the basic science and developments of subthreshold swing technology and recent advancements in the field. The authors discuss the impact of semiconductor materials and architecture designs on TFET devices and the performance and usage of FET devices in various domains such as nanoelectronics, Memory Devices, and biosensing applications. They also cover a variety of FET devices, such as MOSFETs and TFETs, with various structures based on the tunneling transport phenomenon.

The contents of the book have been designed and arranged in such a way that Electrical Engineering students, researchers in the field of nanodevices and device-circuit codesign, as well as industry professionals working in the domain of semiconductor devices, will find the material useful and easy to follow.

Table of Contents:

Chapter 1. Challenges of Conventional Cmos Technology in Perspective of Low Power Applications

Chapter 2. Basic Science and Development of Subthreshold Swing Technology

Chapter 3. Historical Development of MOS technology to Tunnel FETs

Chapter 4. Modeling of Gate Engineered TFETs: Challenges and Opportunities

Chapter 5. Modeling of Gate Engineered TFET: challenges and Opportunities.

Chapter 6. Evolution of Heterojunction Tunnel Field Effect Transistor and its Advantages

Chapter 7. Analog / RF performance analysis of TFET device

Chapter 8. DC Analysis and Analog/HF Performances of GAA-TFET with Dielectric Pocket

Chapter 9. Investigation on Ambipolar Current Suppression in Tunnel FETs

Chapter 10. Analysis of Channel Doping Variation on Transfer Characteristics to High Frequency performance of F-TFET

Chapter 11. Design of Nanotube TFET Biosensor

Chapter 12. TFET-based Memory Cell Design with Top-down Approach

Chapter 13. Designing of nonvolatile memories utilizing Tunnel Field Effect Transistor

Chapter 14. TFET-based Universal

Chapter 15. TFET-based Level Shifter Circuits for Low Power Applications

[Commemorative] History of Junction Technologies

Hiroshi Iwai

History of Junction Technologies

Commemorative talk for the 75th anniversary of the transistor

IWJT 2023; T-Cosponsored by IEEE EDS; 

Kyoto (J) June 8-9, 2023

1 International College of Semiconductor Technology, National Yang Ming Chiao Tung University, Hsinchu, Taiwan
2 Tokyo Institute of Technology, Japan

Abstract: In this paper, I describe the history of junction technologies for ICT (Information and Communication Technology) devices. Junctions serve as functional interfaces between materials in these devices. Over the past 200 years, since the inception of electrical engineering, a wide range of junction technologies have been developed as key components for device operation, playing a significant role in advancing intelligence in human society.

FIG: The first idea of FET (MISFET) by J. Lilienfeld "Method and apparatus for controlling electric current", Canadian Patent CA272437TA, filed October 22, 1925

Acknowledgements: I [author: Hiroshi Iwai] would like to express my sincere appreciation to the Tokyo Institute of Technology Library for granting me access to historically significant documents. The information available on the Computer History Museum (CHM) website was instrumental in understanding the timeline of device development. I am deeply grateful to Prof. Kazuo Tsutsui of Tokyo Institute of Technology for providing me with a conducive environment to concentrate on writing this manuscript. I would also like to extend my gratitude to the IWJT committee members for granting me the valuable opportunity to document the history of junction technologies, logic and memory device technologies, as well as reviewing the lengthy manuscript. In particular, I am grateful to Dr. Michael Current for his meticulous review of the manuscript. Finally, I would like to thank my colleagues in both industry and academia who have dedicated their time and expertise to the advancement of integrated circuit technology over the years.

[paper] Perovskite Photodiodes

Dong Li and Anlian Pan

Perovskite sensitized 2D photodiodes

Light Sci Appl 12, 139 (2023)

DOI: 10.1038/s41377-023-01187-2

Key Laboratory for Micro-Nano Physics and Technology of Hunan Province, State Key Laboratory of Chemo/Biosensing and Chemometrics, Hunan Institute of Optoelectronic Integration, College of Materials Science and Engineering, Hunan University, Changsha, China

Abstract: A new type of perovskite sensitized programmable WSe2 photodiode is constructed based on MAPbI3/WSe2 heterojunction, presenting flexible reconfigurable characteristics and prominent optoelectronic performances. The unique design of MAPbI3/WSe2 device provides a new idea to fabricate high-performance programmable photodiodes. In addition, the combination of atomic thin 2D materials and ionic solids enables effective coupling between electronic transport and ionic transport, which may open up a new pathway for unconventional computing, information storage systems, and programmable optoelectronic devices.

FIG: Schematic view of MAPbI3/WSe2 device structure and working mechanism 

of the programmable perovskite sensitized WSe2 photodiode

[paper] Teaching Traditional TCAD New Tricks

Sanghoon Myung¹, Wonik Jang¹, Seonghoon Jin²

Myung Choe¹, Changwook Jeong¹, and Dae Sin Kim¹

Restructuring TCAD System:

Teaching Traditional TCAD New Tricks

DOI: 10.1109/IEDM19574.2021.9720616

1Data and Information Technology Center, Samsung Electronics.
2Device Lab, Samsung Semiconductor Inc.

Abstract : Traditional TCAD simulation has succeeded in predicting and optimizing the device performance; however, it still faces a massive challenge - a high computational cost. There have been many attempts to replace TCAD with deep learning, but it has not yet been completely replaced. This paper presents a novel algorithm restructuring the traditional TCAD system. The proposed algorithm predicts three-dimensional (3D) TCAD simulation in real-time while capturing a variance, enables deep learning and TCAD to complement each other, and fully resolves convergence errors.

Fig: (a) A TCAD process simulation result. (b) A prediction result of RTT process model.

(c) 1D doping concentration plot in the horizontal direction below the gate.

(d) 1D doping concentration plot in the vertical direction at the center of drain.