[C4P] EDTM Conference 2024, Bangalore

8th IEEE Electron Devices Technology and Manufacturing

EDTM Conference 2024

Theme: Strengthening Globalization in Semiconductors

Hilton Bangalore, India, March 3rd- 6th, 2024

https://ewh.ieee.org/conf/edtm/2024/

Call for Paper: We cordially invite you to submit ORIGINAL 3-page Camera-Ready papers to the 2024 IEEE Electron Devices Technology and Manufacturing (IEEE EDTM 2024) Conference for possible presentations. Original papers are sought on any topic within the scope of IEEE EDTM 2024. There are 14 R&D Tracks for IEEE EDTM 2024, among them:

TRACK 9. Modeling and Simulation (MS)

Advances in modeling/simulation of devices, packages and processes; Technology CAD and benchmarking; Atomistic process and device simulation; Compact models for DTCO and STCO; AI/ML-augmented modelling; Material and interconnect modeling; Models for photonic devices.

Important Dates for Authors

• Three-page camera-ready paper submission starts: August 1,2023
• Paper submission deadline: October 15, 2023 October 30, 2023 
• Notification for Acceptance: December 15, 2023

Accepted IEEE EDTM 2024 papers will be considered for competition for the Best Paper Award, Best Student Paper Awards and Best Poster Awards.

More details on paper submission can be found at the Paper Submission webpage.

[Proceedings] MNDCS 2023

Micro and Nanoelectronics Devices, Circuits and Systems

Select Proceedings of MNDCS 2023

Part of the book series: Lecture Notes in Electrical Engineering (LNEE, volume 1067) DOI: 10.1007/978-981-99-4495-8

Editors: Trupti Ranjan Lenka, Samar K. Saha, Lan Fu

This book presents select proceedings of the International Conference on Micro and Nanoelectronics Devices, Circuits and Systems (MNDCS-2023). The book includes cutting-edge research papers in the emerging fields of micro and nanoelectronics devices, circuits, and systems from experts working in these fields over the last decade. The book is a unique collection of chapters from different areas with a common theme and is immensely useful to academic researchers and practitioners in the industry who work in this field.

[paper] The Future Transistors

Wei Cao, Huiming Bu, Maud Vinet, Min Cao, Shinichi Takagi, Sungwoo Hwang, Tahir Ghani

and Kaustav Banerjee

The future transistors

Nature vol. 620, pp. 501–515 (2023)

DOI: 10.1038/s41586-023-06145-x

Abstract: The metal–oxide–semiconductor field-effect transistor (MOSFET), a core element of complementary metal–oxide–semiconductor (CMOS) technology, represents one of the most momentous inventions since the industrial revolution. Driven by the requirements for higher speed, energy efficiency and integration density of integrated-circuit products, in the past six decades the physical gate length of MOSFETs has been scaled to sub-20 nanometres. However, the downscaling of transistors while keeping the power consumption low is increasingly challenging, even for the state-of-the-art fin field-effect transistors. Here we present a comprehensive assessment of the existing and future CMOS technologies, and discuss the challenges and opportunities for the design of FETs with sub-10-nanometre gate length based on a hierarchical framework established for FET scaling. We focus our evaluation on identifying the most promising sub-10-nanometre-gate-length MOSFETs based on the knowledge derived from previous scaling efforts, as well as the research efforts needed to make the transistors relevant to future logic integrated-circuit products. We also detail our vision of beyond-MOSFET future transistors and potential innovation opportunities. We anticipate that innovations in transistor technologies will continue to have a central role in driving future materials, device physics and topology, heterogeneous vertical and lateral integration, and computing technologies.

FIG: The history of transistor technology.

Acknowledgements: K.B. acknowledges support from the Army Research Office (grant W911NF1810366), the Air Force Office of Scientific Research (grant FA9550-18-1-0448), the Japan Science and Technology Agency CREST Program (grant SB180064) and the National Science Foundation (grant CCF 2132820). K.B. thanks the following individuals for their selfless support during the organization of the collaboration: T. Ernst, CEA-LETI, Grenoble, France; T. Sakurai, The University of Tokyo, Tokyo, Japan; J. Welser, IBM Almaden Research Centre, San Jose, USA. K.B. also thanks S. Oda, Tokyo Institute of Technology, Ōokayama, Japan, for useful discussions.

[11k online viewers] 7th Sino MOS-AK/Nanjing

Arbeitskreis Modellierung von Systemen und Parameterextraktion

Modeling of Systems and Parameter Extraction Working Group

7th Sino MOS-AK Workshop in Nanjing (CN)

August 11-13, 2023 (online/onsite)

Recent, consecutive, 7th Sino MOS-AK/Nanjing Workshop discussing the Compact/SPICE modeling and its Verilog-A Standardization reached 11k online viewers. The MOS-AK participants and online attendees have followed one day SiC-related device modeling training on August 11 featured presentations by experts currently working at Robert Bosch GmbH and then two days workshop with 24 R&D Compact/SPICE modeling presentations:

[paper] 5-DC-parameter MOSFET model

Deni Germano Alves Neto1, Cristina Missel Adornes1, Gabriel Maranhao1, Mohamed Khalil Bouchoucha2,3, Manuel J. Barragan3, Andreia Cathelin2, Marcio Cherem Schneider1, Sylvain Bourdel3 and Carlos Galup-Montoro1

A 5-DC-parameter MOSFET model for circuit simulation in QucsStudio and SPECTRE

2023 21st IEEE Interregional NEWCAS Conference (NEWCAS) 

DOI: 10.1109/NEWCAS57931.2023.10198173

1 Federal University of Santa Catarina, Florianopolis (BR)
2 STMicroelectronics, Crolles (F)
3 Univ. Grenoble Alpes, CNRS, Grenoble INP, TIMA, Grenoble (F)

Abstract: A minimalist MOSFET model for circuit simulation with only five DC parameters written in Verilog-A is presented. The five parameters can be extracted from direct and simple methods in common circuit simulators. The DC characteristics of transistors in both 180-nm bulk CMOS and 28-nm FD-SOI technologies generated by the five-parameter model are compared with those generated by the BSIM and UTSOI2 models, respectively. The simulation of some basic circuits using the proposed 5-DC-parameter MOSFET model shows good matching with the simulation using the BSIM model, at the benefit of a much simpler set of DC parameters.

Fig: DC characteristic gm/ID vs. id used to extract ζ.

REF:

[1] Advanced Compact MOSFET (ACM) in C. M. Adornes, D. G. Alves Neto, M. C. Schneider, and C. Galup-Montoro, “Bridging the gap between design and simulation of low voltage CMOS circuits,” Journal of Low Power Electronics and Applications, vol. 12, no. 2, 2022.